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3D3438x-200 Datasheet(PDF) 3 Page - Data Delay Devices, Inc. |
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3D3438x-200 Datasheet(HTML) 3 Page - Data Delay Devices, Inc. |
3 / 6 page 3D3438 Doc #10005 DATA DELAY DEVICES, INC. 3 7/8/2010 3 Mt. Prospect Ave. Clifton, NJ 07013 APPLICATION NOTES (CONT’D) TRANSPARENT PARALLEL MODE (MD = 1, AE = 1) The eight program pins P0 - P7 directly control the output delay. A change on one or more of the program pins will be reflected on the output delay after a time tPDV, as shown in Figure 2. A register is required if the programming data is bused. LATCHED PARALLEL MODE (MD = 1, AE PULSED) The eight program pins P0 - P7 are loaded by the falling edge of the Enable pulse, as shown in Figure 3. After each change in delay value, a settling time tEDV is required before the input is accurately delayed. SERIAL MODE (MD = 0) While observing data setup (tDSC) and data hold (tDHC) requirements, timing data is loaded in MSB-to-LSB order by the rising edge of the clock (SC) while the enable (AE) is high, as shown in Figure 4. The falling edge of the enable (AE) activates the new delay value which is reflected at the output after a settling time tEDV. As data is shifted into the serial data input (SI), the previous contents of the 8-bit input register are shifted out of the serial output port pin (SO) in MSB-to-LSB order, thus allowing cascading of multiple devices by connecting the serial output pin (SO) of the preceding device to the serial data input pin (SI) of the succeeding device, as illustrated in Figure 5. The total number of serial data bits in a cascade configuration must be eight times the number of units, and each group of eight bits must be transmitted in MSB-to-LSB order. To initiate a serial read, enable (AE) is driven high. After a time tEQV, bit 7 (MSB) is valid at the serial output port pin (SO). On the first rising edge of the serial clock (SC), bit 7 is loaded with the value present at the serial data input pin (SI), while bit 6 is presented at the serial output pin (SO). To retrieve the remaining bits seven more rising edges must be generated on the serial clock line. The read operation is destructive. Therefore, if it is desired that the original delay setting remain unchanged, the read data must be written back to the device(s) before the enable (AE) pin is brought low. The SO pin, if unused, must be allowed to float if the device is configured in the serial programming mode. The serial mode is the only mode available on the 8-pin version of the 3D3438, and this mode is unavailable on the 14-pin version of the 3D3438. PROGRAMMABLE DELAY LINE LATCH 8-BIT INPUT REGISTER MD SC SI AE IN SO OUT P0 P1 P2 P3 P4 P5 P6 P7 MODE SELECT SHIFT CLOCK SERIAL INPUT ADDRESS ENABLE SIGNAL IN SIGNAL OUT SERIAL OUTPUT PARALLEL INPUTS Figure1: Functional block diagram PREVIOUS PREVIOUS NEW VALUE NEW VALUE tPDX tPDV PARALLEL INPUTS P0-P7 DELAY TIME Figure 2: Non-latched parallel mode (MD=1, AE=1) |
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