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ADS5560IRGZR Datasheet(PDF) 9 Page - Texas Instruments |
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ADS5560IRGZR Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 56 page  ADS5560 ADS5562 www.ti.com SLWS207A – MAY 2008 – REVISED MAY 2012 TIMING CHARACTERISTICS – LVDS AND CMOS MODES (1) Typical values are at 25°C, AVDD = 3.3 V, DRVDD = 3.0 to 3.6V, Sampling frequency = 80 MSPS, sine wave input clock, 50% clock duty cycle, 1.5 VPP clock amplitude, CL = 5 pF (2) , no internal termination, I O = 3.5 mA, RL = 100 Ω (3) Min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = DRVDD = 3.0 to 3.6V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ta Aperture delay 0.5 1.2 2 ns Sampling frequency = 80 MSPS 90 fs rms tj Aperture jitter Sampling frequency = 40 MSPS 135 fs rms Time to data stable (4) after coming out of STANDBY mode 60 200 μs Wake-up time Time to valid data after stopping and restarting the input clock 80 μs Clock Latency 16 cycles DDR LVDS MODE(5) LVDS bit clock duty cycle 47% 50% 53% tsu Data setup time(6) Data valid(7) to zero-crossing of CLKOUTP 2.0 3.0 ns th Data hold time(6) Zero-crossing of CLKOUTP to data becoming invalid(7) 2.0 3.0 ns tPDI Clock propagation delay Input clock rising edge cross-over to output clock rising edge cross- 9.5 11 12.5 ns over tr Data rise time Rise time measured from –100 mV to 100 mV 0.15 0.22 0.3 ns tf Data fall time Fall time measured from 100 mV to –100 mV 0.15 0.22 0.3 ns tr Output clock rise time Rise time measured from –100 mV to 100 mV 0.15 0.22 0.3 ns tf Output clock fall time Fall time measured from 100 mV to –100 mV 0.15 0.22 0.3 ns tOE Output enable (OE) to data Time to data valid after OE becomes active 700 ns delay PARALLEL CMOS MODE CMOS output clock duty 50% cycle tsu Data setup time Data valid(8) to 50% of CLKOUT rising edge 6.5 8.0 ns th Data hold time 50% of CLKOUT rising edge to data becoming invalid (8) 2.0 3.0 ns tPDI Clock propagation delay Input clock rising edge cross-over to 50% of CLKOUT rising edge 6.3 7.8 9.3 ns tr Data rise time Rise time measured from 20% to 80% of DRVDD 1.0 1.5 2.0 ns tf Data fall time Fall time measured from 80% to 20% of DRVDD 1.0 1.5 2.0 ns tr Output clock rise time Rise time measured from 20% to 80% of DRVDD 0.7 1.0 1.2 ns tf Output clock fall time Fall time measured from 80% to 20% of DRVDD 1.2 1.5 1.8 ns tOE Output enable (OE) to data Time to data valid after OE becomes active 200 ns delay (1) Timing parameters are ensured by design and characterization and not tested in production. (2) CL is the effective external single-ended load capacitance between each output pin and ground. (3) Io refers to the LVDS buffer current setting; RL is the differential load resistance between the LVDS output pair. (4) Data stable is defined as the point at which the SNR is within 2dB of its normal value. (5) Measurements are done with a transmission line of 100 Ω characteristic impedance between the device and the load. (6) Setup and hold time specifications take into account the effect of jitter on the output data and clock. (7) Data valid refers to logic high of +100 mV and logic low of -100 mV. (8) Data valid refers to logic high of 2.6 V and logic low of 0.66 V. Copyright © 2008–2012, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Link(s): ADS5560 ADS5562 |
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