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AOZ1361DI Datasheet(PDF) 9 Page - Alpha & Omega Semiconductors |
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AOZ1361DI Datasheet(HTML) 9 Page - Alpha & Omega Semiconductors |
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9 / 12 page  AOZ1361DI Rev. 2.0 October 2010 www.aosmd.com Page 9 of 12 Applications Information Input Capacitor Selection The input capacitor prevents large voltage transients from appearing at the input, and provides the instantaneous current needed each time the switch turns on and to limit input voltage drop. Also it is to prevent high-frequency noise on the power line from passing through the output of the power side. The choice of the input capacitor is based on its ripple current and voltage ratings rather than its capacitor value. The input capacitor should be located as close to the VIN pin as possible. A 1µF ceramic cap is recommended. However, higher capacitor values further reduce the voltage drop at the input. Output Capacitor Selection The output capacitor acts in a similar way. A small 0.1µF capacitor prevents high-frequency noise from going into the system. Also, the output capacitor has to supply enough current for a large load that it may encounter during system transients. This bulk capacitor must be large enough to supply fast transient load in order to prevent the output from dropping. Current Limit Setting The current limit is program by using external resistor connected to the SET pin. To set the current limit, use the Figure 3 below. Figure 3. Current Limit vs. RSET (VIN = 12V) Slew Rate Setting Slew rate is set by changing the capacitor value on the SS pin of the device. A capacitor connected between this SS pin and ground will reduce the output slew-rate. The capacitive range is 0.001µF to 0.1µF. See Figure 4 for Output Slew Rate Adjustment vs. Capacitance. Figure 4. Output Slew Rate Adjustment vs. Capacitance Power Dissipation Calculation Calculate the power dissipation for normal load condition using the following equation: PD = RON x (IOUT) 2 The worst case power dissipation occurs when the load current hits the current limit due to over-current or short circuit faults. The power dissipation under these conditions can be calculated using the following equation: PD = (VIN – VOUT) x ILIMIT Layout Guidelines Good PCB layout is important for improving the thermal and overall performance of AOZ1361. To optimize the switch response time to output short-circuit conditions keep all traces as short as possible to reduce the effect of unwanted parasitic inductance. Place the input and output bypass capacitors as close as possible to the IN and OUT pins. The input and output PCB traces should be as wide as possible for the given PCB space. Use a ground plane to enhance the power dissipation capability of the device. AOZ1361 RSET vs. ILIM 1.8 2.8 3.8 4.8 5.8 6.8 15 35 55 75 95 115 RSET (kΩ) 0 5 10 15 20 25 30 35 0 0.02 0.04 0.06 0.08 0.1 Capacitance (μF) |
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