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EM638165TS-10 Datasheet(PDF) 11 Page - Etron Technology, Inc. |
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EM638165TS-10 Datasheet(HTML) 11 Page - Etron Technology, Inc. |
11 / 71 page EtronTech EM638165 Preliminary 11 Rev 0.6 Feb. 2001 RAS# T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CL K CKE CS# CAS# WE# A11 A10 A0-A9 DQM DQ tCK2 Clock min. Address Key tRP Hi-Z PrechargeAll Mode Register Set Command Any Command Mode Register Set Cycle (CAS# Latency = 2, 3) The mode register is divided into various fields depending on functionality. Address BS0,1 A11,10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Function RFU* RFU* WBL Test Mode CAS Latency BT Burst Length *Note: RFU (Reserved for future use) should stay “0” during MRS cycle. • Burst Length Field (A2~A0) This field specifies the data length of column access using the A2~A0 pins and selects the Burst Length to be 2, 4, 8, or full page. A2 A1 A0 Burst Length 0 0 0 1 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Full Page |
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