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EM636327JT-8 Datasheet(PDF) 10 Page - Etron Technology, Inc.

Part # EM636327JT-8
Description  512K x 32 High Speed Synchronous Graphics DRAM(SGRAM)
Download  78 Pages
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Manufacturer  ETRON [Etron Technology, Inc.]
Direct Link  http://www.etron.com
Logo ETRON - Etron Technology, Inc.

EM636327JT-8 Datasheet(HTML) 10 Page - Etron Technology, Inc.

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EtronTech
EM636327
Preliminary
10
December
1998
DSF
BankActivate
command
D
CK
Q
DQM0
MR7
MR6
MR5
MR4
MR3
MR2
MR1
MR0
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
DRAM
CELL
0 = Masked
1 = Not Masked
Note: Only the lower byte is shown. The operation is identical for other bytes.
Write Per Bit (I/O Mask) Block Diagram
A write burst without the auto precharge function may be interrupted by a subsequent
Write/Block Write, BankPrecharge/PrechargeAll, or Read command before the end of the burst
length. An interrupt coming from Write/Block Write command can occur on any clock cycle
following the previous Write command (refer to the following figure).
CLK
C OM M A ND
T0
T1
T2
T3
T4
T5
T6
T7
T8
DIN B2
NOP
WRITE A
NOP
NOP
NOP
NOP
NOP
WRITE B
NOP
DIN A0
DIN B0
DIN B1
DQ's
DIN B3
1 Clk Interval
Write Interrupted by a Write (Burst Length = 4, CAS# Latency = 1, 2, 3)
The Read command that interrupts a write burst without auto precharge function should be
issued one cycle after the clock edge in which the last data-in element is registered. In order to
avoid data contention, input data must be removed from the DQs at least one clock cycle before the


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