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PI6C10806B Datasheet(PDF) 5 Page - Pericom Semiconductor Corporation |
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PI6C10806B Datasheet(HTML) 5 Page - Pericom Semiconductor Corporation |
5 / 13 page 5 PS9038C 06/29/10 PI6C10806B 1.8V/2.5V/3.3V, 100MHz, Low Skew 1:6 Crystal to LVCMOS Clock Buffer Storage Temperature...........................................................–65°C to +150°C VDD, VDDO Voltage...............................................................–0.5V to +3.6V Output Voltage (max. 3.6V) .......................................... –0.5V to VDD+0.5V Input Voltage (max 3.6V).............................................. –0.5V to VDD+0.5V 2.5V Absolute Maximum Ratings (Above which the useful life may be impaired. For user guidelines only, not tested.) Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating condi- tions for extended periods may affect reliability. 2.5V I/O DC Characteristics (Over Operating Range: VDD = 2.5V ± 5%, TA = -40° to 85°C) Parameters Description Test Conditions(1) Min. Typ. (2) Max. Units VDDO I/O Supply Voltage 2.375 2.5 2.625 VIH Input HIGH Voltage Logic HIGH level 1.7 VDD+0.3 V VIL Input LOW Voltage Logic LOW level -0.3 0.7 VOH Output High Voltage VDDO = Min., VIN = VIH or VIL IOH = -1mA 2 V IOH = -8mA 2 VOL Output LOW Voltage VDDO = Min., VIN = VIH or VIL IOL = 1mA 0.4 IOL = 8mA 0.4 Notes: 1. For Max. or Min. conditions, use appropriate operating range values. 2. Typical values are at VDD =3.3V, +25°C ambient and maximum loading. 2.5V I/O AC Characteristics (Over Operating Range: VDD/VDDO = 2.5V ± 5%, TA = -40° to 85°C) Parameters Description Test Conditions(1) Min. Typ Max. Units fOUT Output Frequency Using Crystal 10 50 MHz External Clock(2) 0 100 tDC Output Duty Cycle @ VDDO/2 47 55 % tR/tF CLKn Rise/Fall Time 20% to 80% 150 800 ps RMS Random RMS Phase Jitter 25MHz @ Integration Range 100Hz - 1MHz 0.112 ps tSK(O)(3) Output to Output Skew between any two outputs of the same device @ same transition @VDDO/2 80 ps tDIS,tEN( 4) Output Enable/Disable @VDDO/2 4 cycles Notes: 1. Unless noted otherwise, all parameters are tested with xtal @ f <= Fxtal_max,; outputs are terminated @ 50Ω to VDDO/2, see waveforms. 2. External clock source is driving XTAL_IN input 3. Identical conditions: loading, transitions, supply voltage, temperature, package type and speed grade. 4. These parameters are guaranteed, but not tested. Max delay is 4 cycles. Min. setup time = 3ns. 10-0151 |
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