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AT25DF321A Datasheet(PDF) 11 Page - ATMEL Corporation |
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AT25DF321A Datasheet(HTML) 11 Page - ATMEL Corporation |
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11 / 52 page  11 3686D–DFLASH–12/09 Atmel AT25DF321A While the device is programming, the Status Register can be read and will indicate that the device is busy. For faster throughput, it is recommended that the Status Register be polled rather than waiting the t BP or tPP time to determine if the data bytes have finished programming. At some point before the program cycle completes, the WEL bit in the Status Register will be reset back to the logical “0” state. The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to program properly. If a programming error arises, it will be indicated by the EPE bit in the Status Register. Figure 8-1. Byte Program Figure 8-2. Page Program 8.2 Dual-Input Byte/Page Program The Dual-Input Byte/Page Program command is similar to the standard Byte/Page Program command and can be used to program anywhere from a single byte of data up to 256-bytes of data into previously erased memory locations. Unlike the standard Byte/Page Program command, however, the Dual-Input Byte/Page Program command allows two bits of data to be clocked into the device on every clock cycle rather than just one. Before the Dual-Input Byte/Page Program command can be started, the Write Enable command must have been previously issued to the device (see “Write Enable” on page 18) to set the Write Enable Latch (WEL) bit of the Status Register to a logical “1” state. To perform a Dual-Input Byte/Page Program command, an opcode of A2h must be clocked into the device followed by the three address bytes denoting the first byte location of the memory array to begin programming at. After the address bytes have been clocked in, data can then be clocked into the device two bits at a time on both the SOI and SI pins. The data is always input with the MSB of a byte first, and the MSB is always input on the SOI pin. During the first clock cycle, bit 7 of the first data byte would be input on the SOI pin while bit 6 of the same data byte would be input on the SI pin. During the next clock cycle, bits 5 and 4 of the first data byte would be input on the SOI and SI pins, respectively. The sequence would continue with each byte of data being input after every four clock cycles. Like the standard Byte/Page Program command, all data clocked into the device is stored in an internal buffer. SCK CS SI SO MSB MSB 23 1 0 00000010 67 5 410 11 9 812 39 37 38 33 36 35 34 31 32 29 30 OPCODE HIGH-IMPEDANCE AAAA AAA A A MSB DDDDDDD D ADDRESS BITS A23-A0 DATA IN SCK CS SI SO MSB MSB 23 1 0 00000010 67 5 49 839 37 38 33 36 35 34 31 32 29 30 OPCODE HIGH-IMPEDANCE AA AAA A MSB DDDDDDD D ADDRESS BITS A23-A0 DATA IN BYTE 1 MSB DDDDDDD D DATA IN BYTE n |
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