11

AT25DN512C

DS-25DN512C–037C–5/2014

D8h is used for a 32-Kbyte erase. Before a Block Erase command can be started, the Write Enable command must have

been previously issued to the device to set the WEL bit of the Status Register to a logical “1” state.

To perform a Block Erase, the CS pin must first be asserted and the appropriate opcode (20h, 52h, or D8h) must be

clocked into the device. After the opcode has been clocked in, the three address bytes specifying an address within the

4- or 32-Kbyte block to be erased must be clocked in. Any additional data clocked into the device will be ignored. When

the CS pin is deasserted, the device will erase the appropriate block. The erasing of the block is internally self-timed and

should take place in a time of t

Since the Block Erase command erases a region of bytes, the lower order address bits do not need to be decoded by the

device. Therefore, for a 4-Kbyte erase, address bits A11-A0 will be ignored by the device and their values can be either a

logical “1” or “0”. For a 32-Kbyte erase, address bits A14-A0 will be ignored by the device. Despite the lower order

address bits not being decoded by the device, the complete three address bytes must still be clocked into the device

before the CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits);

otherwise, the device will abort the operation and no erase operation will be performed.

If the memory is in the protected state, then the Block Erase command will not be executed, and the device will return to

the idle state once the CS pin has been deasserted.

The WEL bit in the Status Register will be reset back to the logical “0” state if the erase cycle aborts due to an incomplete

address being sent, the CS pin being deasserted on uneven byte boundaries, or because a memory location within the

region to be erased is protected.

While the device is executing a successful erase cycle, the Status Register can be read and will indicate that the device

is busy. For faster throughput, it is recommended that the Status Register be polled rather than waiting the t

determine if the device has finished erasing. At some point before the erase cycle completes, the WEL bit in the Status

Register will be reset back to the logical “0” state.

The device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase properly. If

an erase error occurs, it will be indicated by the EPE bit in the Status Register.

Figure 8-3.

Block Erase

8.4

Chip Erase

The entire memory array can be erased in a single operation by using the Chip Erase command. Before a Chip Erase

command can be started, the Write Enable command must have been previously issued to the device to set the WEL bit

of the Status Register to a logical “1” state.

Three opcodes (60h, 62h, and C7h) can be used for the Chip Erase command. There is no difference in device

functionality when utilizing the three opcodes, so they can be used interchangeably. To perform a Chip Erase, one of the

three opcodes must be clocked into the device. Since the entire memory array is to be erased, no address bytes need to

be clocked into the device, and any data clocked in after the opcode will be ignored. When the CS pin is deasserted, the

device will erase the entire memory array. The erasing of the device is internally self-timed and should take place in a

time of t

SCK

CS

SI

SO

MSB

MSB

23

1

0

CCCCCCCC

67

5

410 11

9

812

31

29 30

27 28

26

OPCODE

AAAA

AAA

A

A

A

A

A

ADDRESS BITS A23-A0

HIGH-IMPEDANCE