6

AT25DN512C

DS-25DN512C–037C–5/2014

5.1

Dual Output Read

The ATx features a Dual-Output Read mode that allow two bits of data to be clocked out of the device every clock cycle

to improve throughput. To accomplish this, both the SI and SO pins are utilized as outputs for the transfer of data bytes.

With the Dual-Output Read Array command, the SI pin becomes an output along with the SO pin.

6.

Commands and Addressing

A valid instruction or operation must always be started by first asserting the CS pin. After the CS pin has been asserted,

the host controller must then clock out a valid 8-bit opcode on the SPI bus. Following the opcode, instruction dependent

information such as address and data bytes would then be clocked out by the host controller. All opcode, address, and

data bytes are transferred with the most-significant bit (MSB) first. An operation is ended by deasserting the CS pin.

Opcodes not supported by the AT25DN512C will be ignored by the device and no operation will be started. The device

will continue to ignore any data presented on the SI pin until the start of the next operation (CS pin being deasserted and

then reasserted). In addition, if the CS pin is deasserted before complete opcode and address information is sent to the

device, then no operation will be performed and the device will simply return to the idle state and wait for the next

operation.

Addressing of the device requires a total of three bytes of information to be sent, representing address bits A23-A0.

Since the upper address limit of the AT25DN512C memory array is 00FFFFh, address bits A23-A16 are always ignored

by the device.

Table 6-1.

Command Listing

Command

Opcode

Clock

Frequency

Address

Bytes

Dummy

Bytes

Data

Bytes

Read Commands

Read Array

0Bh

0000 1011

Up to 104MHz

3

1

1+

03h

0000 0011

Up to 33MHz

3

0

1+

Dual Output Read

3Bh

0011 1011

Up to 50MHz

3

1

1+

Program and Erase Commands

Page Erase

81h

1000 0001

Up to 104MHz

3

0

0

Block Erase (4 Kbytes)

20h

0010 0000

Up to 104MHz

3

0

0

Block Erase (32 Kbytes)

52h

0101 0010

Up to 104MHz

3

0

0

D8h

1101 1000

Up to 104MHz

3

0

0

Chip Erase

60h

0110 0000

Up to 104MHz

0

0

0

C7h

1100 0111

Up to 104MHz

0

0

0

Chip Erase (Legacy Command)

62h

0110 0010

Up to 104MHz

0

0

0

Byte/Page Program (1 to 256 Bytes)

02h

0000 0010

Up to 104MHz

3

0

1+

Protection Commands

Write Enable

06h

0000 0110

Up to 104MHz

0

0

0

Write Disable

04h

0000 0100

Up to 104MHz

0

0

0

Security Commands

Program OTP Security Register

9Bh

1001 1011

Up to 104MHz

3

0

1+