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AT25DN512C-XMHF-B Datasheet(PDF) 1 Page - List of Unclassifed Manufacturers |
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AT25DN512C-XMHF-B Datasheet(HTML) 1 Page - List of Unclassifed Manufacturers |
1 / 41 page DS-25DN512C–037C–5/2014 Features Single 2.3V - 3.6V Supply Serial Peripheral Interface (SPI) Compatible Supports SPI Modes 0 and 3 Supports Dual Output Read 104MHz Maximum Operating Frequency Clock-to-Output (t V) of 6ns Flexible, Optimized Erase Architecture for Code + Data Storage Applications Uniform 256-Byte Page erase Uniform 4-Kbyte Block Erase Uniform 32-Kbyte Block Erase Full Chip Erase Hardware Controlled Locking of Protected Sectors via WP Pin 128-Byte Programmable OTP Security Register Flexible Programming Byte/Page Program (1 to 256 Bytes) Fast Program and Erase Times 1.5ms Typical Page Program (256 Bytes) Time 40ms Typical 4-Kbyte Block Erase Time 320ms Typical 32-Kbyte Block Erase Time Automatic Checking and Reporting of Erase/Program Failures Software Controlled Reset JEDEC Standard Manufacturer and Device ID Read Methodology Low Power Dissipation 350nA Ultra Deep Power Down current (Typical) 5µA Deep Power-Down Current (Typical) 25uA Standby current (Typical) 6mA Active Read Current (Typical) Endurance: 100,000 Program/Erase Cycles Data Retention: 20 Years Complies with Full Industrial Temperature Range Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options 8-lead SOIC (150-mil) 8-pad Ultra Thin DFN (2 x 3 x 0.6mm) 8-lead TSSOP Package AT25DN512C 512-Kbit, 2.3V Minimum SPI Serial Flash Memory with Dual-Read Support PRELIMINARY DATASHEET |
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