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MCIMX6U8DVM10AC Datasheet(PDF) 8 Page - Freescale Semiconductor, Inc |
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MCIMX6U8DVM10AC Datasheet(HTML) 8 Page - Freescale Semiconductor, Inc |
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8 / 168 page  i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 3 8 Freescale Semiconductor Architectural Overview • CSU—Central Security Unit. Enhancement for the IC Identification Module (IIM). Will be configured during boot and by eFUSEs and will determine the security level operation mode as well as the TZ policy. • A-HAB—Advanced High Assurance Boot—HABv4 with the new embedded enhancements: SHA-256, 2048-bit RSA key, version control mechanism, warm boot, CSU, and TZ initialization. NOTE The actual feature set depends on the part numbers as described in Table 1, "Example Orderable Part Numbers," on page 3. Functions, such as video hardware acceleration, and 2D and 3D hardware graphics acceleration may not be enabled for specific part numbers. 1.3 Updated Signal Naming Convention The signal names of the i.MX6 series of products have been standardized to better align the signal names within the family and across the documentation. Some of the benefits of these changes are as follows: • The names are unique within the scope of an SoC and within the series of products • Searches will return all occurrences of the named signal • The names are consistent between i.MX 6 series products implementing the same modules • The module instance is incorporated into the signal name This change applies only to signal names. The original ball names have been preserved to prevent the need to change schematics, BSDL models, IBIS models, etc. Throughout this document, the updated signal names are used except where referenced as a ball name (such as the Functional Contact Assignments table, Ball Map table, and so on). A master list of the signal name changes is in the document, IMX 6 Series Signal Name Mapping (EB792). This list can be used to map the signal names used in older documentation to the new standardized naming conventions. 2 Architectural Overview The following subsections provide an architectural overview of the i.MX 6Solo/6DualLite processor system. 2.1 Block Diagram Figure 2 shows the functional modules in the i.MX 6Solo/6DualLite processor system. |
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