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FIN1218 Datasheet(PDF) 11 Page - Fairchild Semiconductor |
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FIN1218 Datasheet(HTML) 11 Page - Fairchild Semiconductor |
11 / 20 page © 2003 Fairchild Semiconductor Corporation www.fairchildsemi.com FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 11 Receiver AC Electrical Characteristics Values are at over supply voltages and operating temperatures, unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Units tRCOL RxCLKOut LOW Time Figure 12 Rising Edge Strobe f=40MHz 10.0 11.0 ns tRCOH RxCLKOut HIGH Time 10.0 12.2 ns tRSRC RxOut Valid Prior to RxCLKOut 6.5 11.6 ns tRHRC RxOut Valid After RxCLKOut 6.0 11.6 ns tRCOP Receiver Clock Output (RxCLKOut) Period Figure 12 Rising Edge Strobe f=65MHz 15.0 T 50.0 ns tRCOL RxCLKOut LOW Time 5.0 7.8 9.0 ns tRCOH RxCLKOut HIGH Time 5.0 7.3 9.0 ns tRSRC RxOut Valid Prior to RxCLKOut 4.5 7.7 ns tRHRC RxOut Valid After RxCLKOut 4.0 8.4 ns tRCOP Receiver Clock Output (RxCLKOut) Period Figure 12 Rising Edge Strobe f=85MHz FIN1218 only 11.76 T 50.00 ns tRCOL RxCLKOut LOW Time 4.0 6.3 6.0 ns tRCOH RxCLKOut HIGH Time 4.5 5.4 6.5 ns tRSRC RxOut Valid Prior to RxCLKOut 3.5 6.3 ns tRHRC RxOut Valid After RxCLKOut 3.5 6.5 ns tROLH Output Rise Time (20% to 80%) CL=8pF, Figure 9 2.2 5.0 ns tROHL Output Fall Time (80% to 20%) 2.1 5.0 ns tRCCD Receiver Clock Input to Clock Output Delay TA=25°C, VCC=3.3V Figure 14 (Error! Reference source not found.) 3.5 6.9 7.5 ns tRPDD Receiver Power-Down Delay Figure 18 1.0 ms tRSPB0 Receiver Input Strobe Position of Bit 0 Figure 21 f=40MHz 1.00 2.15 ns tRSPB1 Receiver Input Strobe Position of Bit 1 4.5 5.8 ns tRSPB2 Receiver Input Strobe Position of Bit 2 8.10 9.15 ns tRSPB3 Receiver Input Strobe Position of Bit 3 11.6 12.6 ns tRSPB4 Receiver Input Strobe Position of Bit 4 15.1 16.3 ns tRSPB5 Receiver Input Strobe Position of Bit 5 18.8 19.9 ns tRSPB6 Receiver Input Strobe Position of Bit 6 22.5 23.6 ns Continued on following page… |
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