© 2003 Fairchild Semiconductor Corporation

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FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3

4

Receivers

Pin Configuration

Figure 4. FIN1216 / FIN1218 (3:21 Receiver)

Pin Definitions

Pin Names

I/O

Type

# of

Pins

Description of Signals

RxIn

I

3

Negative LVDS Differential Data Output

RxIn+

I

3

Positive LVDS Differential Data Output

RxCLKIn-

I

1

Negative LVDS Differential Clock Output

RxCLKIn+

I

1

Positive LVDS Differential Clock Output

RxOut-

O

21

LVTTL Level Data Outputs Goes HIGH for /PwrDn LOW

RxCLKOut

O

1

LVTTL Level Clock Output

/PwrDn

I

1

LVTTL Level Input; Refer to Transmitter and Receiver Power-up and Power-down

Operation Truth Table

I

1

Power Supply Pin for PLL

PLL GND

I

2

Ground Pins for PLL

I

1

Power Supply Pins for LVDS Inputs

LVDS GND

I

3

Ground Pin for LVDS Inputs

I

4

Power Supply Pins for LVTTL Outputs

GND

I

5

Ground Pins for LVTTL Outputs

NC

No Connect