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L1PMPPA25 Datasheet(PDF) 8 Page - Texas Instruments |
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L1PMPPA25 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 222 page  OMAP-L137 SPRS563G – SEPTEMBER 2008 – REVISED JUNE 2014 www.ti.com 3 Device Overview 3.1 Device Characteristics Table 3-1 provides an overview of the OMAP-L137 low power applications processor. The table shows significant features of the device, including the capacity of on-chip RAM, peripherals, and the package type with pin count. Table 3-1. Characteristics of the OMAP-L137 Processor HARDWARE FEATURES OMAP-L137 EMIFB 16/32bit, up to 256MB SDRAM Asynchronous (8/16-bit bus width) RAM, Flash, 16bit up to 128MB SDRAM, NOR, EMIFA NAND Flash Card Interface MMC and SD cards supported. EDMA3 32 independent channels, 8 QDMA channels, 2 Transfer controllers 2 64-Bit General Purpose (each configurable as 2 separate 32-bit timers, 1 configurable Timers as Watch Dog) UART 3 (one with RTS and CTS flow control) SPI 2 (each with one hardware chip select) I2C 2 (both Master/Slave) Multichannel Audio Peripherals 3 (each with transmit/receive, FIFO buffer, 16/12/4 serializers) Serial Port [McASP] Not all peripherals pins 10/100 Ethernet MAC are available at the with Management Data 1 (RMII Interface) same time (for more I/O detail, see the Device Configurations section). eHRPWM 6 Single Edge, 6 Dual Edge Symmetric, or 3 Dual Edge Asymmetric Outputs eCAP 3 32-bit capture inputs or 3 32-bit auxiliary PWM outputs eQEP 2 32-bit QEP channels with 4 inputs/channel UHPI 1 (16-bit multiplexed address/data) USB 2.0 (USB0) High-Speed OTG Controller with on-chip OTG PHY USB 1.1 (USB1) Full-Speed OHCI (as host) with on-chip PHY General-Purpose 8 banks of 16-bit Input/Output Port LCD Controller 1 PRU Subsystem 2 Programmable PRU Cores (PRUSS) Size (Bytes) 488KB RAM DSP 32KB L1 Program (L1P)/Cache (up to 32KB) 32KB L1 Data (L1D)/Cache (up to 32KB) 256KB Unified Mapped RAM/Cache (L2) DSP Memories can be made accessible to ARM, EDMA3, and other peripherals. On-Chip Memory ARM Organization 16KB I-Cache 16KB D-Cache 8KB RAM (Vector Table) 64KB ROM ADDITIONAL SHARED MEMORY 128KB RAM C674x CPU ID + CPU Control Status Register 0x1400 Rev ID (CSR.[31:16]) C674x Megamodule Revision ID Register 0x0000 Revision (MM_REVID[15:0]) 0x0B7D F02F (Silicon Revision 1.0) JTAG BSDL_ID DEVIDR0 register 0x8B7D F02F (Silicon Revision 1.1) 0x9B7D F02F (Silicon Revisions 3.0, 2.1, and 2.0) 8 Device Overview Copyright © 2008–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: OMAP-L137 |
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