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L1DMPPA18 Datasheet(PDF) 4 Page - Texas Instruments |
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L1DMPPA18 Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 222 page  Switched Central Resource (SCR) BOOT ROM 256KB L2 RAM 32KB L1 RAM 32KB L1 Pgm 16KB I-Cache 16KB D-Cache AET 4KB ETB C674x DSP CPU ARM926EJ-S CPU With MMU DSP Subsystem ARM Subsystem JTAG Interface System Control Input Clock(s) 64KB ROM 8KB RAM (Vector Table) Power/Sleep Controller Memory Protection Pin Multiplexing RTC/ 32-kHz OSC PLL/Clock Generator w/OSC General- Purpose Timer General- Purpose Timer (Watchdog) Serial Interfaces I C (2) 2 SPI (2) UART (3) Audio Ports McASP w/FIFO (3) DMA Peripherals Display Internal Memory LCD Ctlr 128KB RAM External Memory Interfaces Connectivity EDMA3 Control Timers eHRPWM (3) eCAP (3) eQEP (2) (10/100) EMAC (RMII) MDIO USB1.1 OHCI Ctlr PHY USB2.0 OTG Ctlr PHY HPI MMC/SD (8b) EMIFA(8b/16B) NAND/Flash 16b SDRAM EMIFB SDRAM Only (16b/32b) GPIO PRU Subsystem OMAP-L137 SPRS563G – SEPTEMBER 2008 – REVISED JUNE 2014 www.ti.com 1.4 Functional Block Diagram Note: Not all peripherals are available at the same time due to multiplexing. Figure 1-1. OMAP-L137 Functional Block Diagram 4 OMAP-L137 Low-Power Applications Processor Copyright © 2008–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: OMAP-L137 |
Similar Part No. - L1DMPPA18 |
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Similar Description - L1DMPPA18 |
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