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PSMN2R7-30BL Datasheet(PDF) 7 Page - NXP Semiconductors |
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PSMN2R7-30BL Datasheet(HTML) 7 Page - NXP Semiconductors |
7 / 15 page PSMN2R7-30BL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 1 — 21 March 2012 7 of 15 NXP Semiconductors PSMN2R7-30BL N-channel 30 V 3.0 m Ω logic level MOSFET in D2PAK tr rise time VDS =15V; RL =0.5 Ω; VGS =4.5 V; RG(ext) =4.7 Ω -82 -ns td(off) turn-off delay time - 74 - ns tf fall time - 35 - ns Source-drain diode VSD source-drain voltage IS =25A; VGS =0V; Tj =25°C; see Figure 17 -0.7 1.2 V trr reverse recovery time IS =25A; dIS/dt = -100 A/µs; VGS =0V; VDS =15V -40 -ns Qr recovered charge - 33 - nC Table 7. Characteristics …continued Tested to JEDEC standards where applicable. Symbol Parameter Conditions Min Typ Max Unit Fig 5. Input and reverse transfer capacitances as a function of gate-source voltage; typical values Fig 6. Forward transconductance as a function of drain current; typical values 003aad410 0 2000 4000 6000 8000 0369 12 VGS (V) C (pF) Ciss Crss 003aad411 0 30 60 90 120 150 180 0 25 50 75 100 ID (A) gfs (S) |
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