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ADC12QS065 Datasheet(PDF) 10 Page - Texas Instruments

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Part # ADC12QS065
Description  Quad 12-Bit 65 MSPS A/D Converter with LVDS Serialized Outputs
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADC12QS065 Datasheet(HTML) 10 Page - Texas Instruments

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VA
AGND
To Internal Circuitry
I/O
ADC12QS065
SNOSAD6H – JULY 2005 – REVISED MARCH 2007
www.ti.com
LVDS Electrical Characteristics
Unless otherwise specified, the following specifications apply for AGND = DGND = DRGND = 0V, VA = VD = +3.3V, VDR=
+2.5V, External VREF = +1.0V, fCLK = 65 MHz, fIN = 5 MHz, CL = 15 pF/pin. Boldface limits apply for TJ = TMIN to TMAX: all
other limits TJ = 25°C
(1) (2) (3) (4)
Units
Symbol
Parameter
Conditions
Typical(5)
Limits(5)
(Limits)
LVDS DC CHARACTERISTICS
Output Differential Voltage
230
mV (min)
VOD
RL = 100Ω
290
(DO+) - (DO-)
450
mV (max)
delta
Output Differential Voltage Unbalance
RL = 100Ω
±1
±15
mV (max)
VOD
1.125
V (min)
VOS
Offset Voltage
RL = 100Ω
1.25
1.375
V (max)
delta VOS Offset Voltage Unbalance
RL = 100Ω
±7
±25
mV (max)
IOS
Output Short Circuit Current
DO = 0V, VIN = 1.1V
-10
mA (max)
LVDS OUTPUT TIMING AND SWITCHING CHARACTERISTICS
tOCP
Output Clock Period
50% to 50%
2.56
ns
35
% (min)
tOCDC
Output Clock Duty Cycle
See(6)
50
65
% (max)
Data Edge to Output Clock Edge Hold
tH
50% to 50%(6)
625
300
ps
Time
Data Edge to Output Clock Edge Set-Up
tS
50% to 50%(6)
600
300
ps
Time
tFP
Frame Period
50% to 50%
15.38
ns
45
% (min)
tFDC
Frame Clock Duty Cycle
See(6)
50
55
% (max)
tDFS
Data Edge to Frame Edge Skew
50% to 50%
60
160
ps (max)
tR, tF
LVDS Rise/Fall Time
CL=5pF to GND, ROUT=100Ω
360
700
ps (max)
tPLD
Serializer PLL Lock Time
50
µs
tSD
Serializer Delay
RL=100Ω
2.76
ns
(1)
The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided
current is limited per. However, errors in the A/D conversion can occur if the input goes above VA or below GND by more than 100 mV.
As an example, if VA is +3.3V, the full-scale input voltage must be ≤+3.4V to ensure accurate conversions.
(2)
To guarantee accuracy, it is required that |VA–VD| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.
(3)
With the test condition for VREF = +1.0V (2VP-P differential input), the 12-bit LSB is 488 µV.
(4)
When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND, or VIN > VA), the current at that pin should be
limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies
with an input current of 25 mA to two.
(5)
Typical figures are at TA = 25°C, and represent most likely parametric norms at the time of product characterization. The typical
specifications are not guaranteed.
(6)
This parameter is guaranteed by design and/or qualification and is not tested in production.
10
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