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DS64EV100 Datasheet(PDF) 4 Page - Texas Instruments |
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DS64EV100 Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 15 page  DS64EV100 SNLS232D – OCTOBER 2007 – REVISED APRIL 2008 www.ti.com Typ Symbol Parameter Conditions Min Max Units (1) VOH High Level Output IOH = –3 mA, VDD3.3 2.4 V Voltage IOH = –3 mA, VDD2.5 2.0 V VOL Low Level Output IOL = 3 mA 0.4 V Voltage IIN Input Current VIN = VDD +1.8 +15 µA VIN = GND −15 0 µA IIN-P Input Leakage VIN = GND, with internal pull-down resistors +95 µA Current with Internal VIN = GND, with internal pull-up resistors Pull-Down/Up –20 µA Resistors CML RECEIVER INPUTS (IN+, IN −) VTX Source Transmit AC-Coupled or DC-Coupled Requirement, Launch Signal Level Differential measurement at point A. 400 1600 mVP-P (IN diff) (Figure 1) VINTRE Input Threshold Differential measurement at point B . 120 mVP-P Voltage (Figure 1) VDDTX Supply Voltage of DC-Coupled Requirement 1.6 VDD V Transmitter to EQ VICMDC Input Common-Mode DC-Coupled Requirement Differential Voltage measurement at point A. VDDTX-0.8 VDDTX-0.2 V (Figure 1), (Note 7) RLI Differential Input 100 MHz – 3.2 GHz, with fixture’s effect de- 10 dB Return Loss embedded RIN Input Resistance Differential Across IN+ and IN-. (Figure 4) 85 100 115 Ω CML OUTPUTS (OUT+, OUT −) VOD Output Differential Differential measurement with OUT+ and OUT- Voltage Level (OUT terminated by 50 Ω to GND, AC-Coupled 550 620 725 mVP-P diff) (Figure 2) VOCM Output Common- Single-ended measurement DC-Coupled with Mode Voltage 50 Ω terminations VDD-0.2 VDD-0.1 V (Note 7) tR, tF Transition Time 20% to 80% of differential output voltage, measured within 1” from output pins. 20 60 ps (Figure 2) (Note 7) RO Output Resistance Single-ended to VDD 42 50 58 Ω RLO Differential Output 100 MHz – 1.6 GHz, with fixture’s effect de- 10 dB Return Loss embedded. IN+ = static high. tPLHD Differential Low to Propagation delay measurement at 50% VOD High Propagation between input to output, 100 Mbps 240 ps Delay (Figure 3), (Note 7) tPHLD Differential High to Low Propagation 240 ps Delay EQUALIZATION DJ1 Residual 30” of 6 mil microstrip FR4, EQ Setting 0x06, Deterministic Jitter at PRBS-7 (27-1) pattern 0.20 UIP-P 10 Gbps (Note 5, 6) DJ2 Residual 40” of 6 mil microstrip FR4, EQ Setting 0x06, Deterministic Jitter at PRBS-7 (27-1) pattern 0.17 0.26 UIP-P 6.4 Gbps (Note 5, 6) DJ3 Residual 40” of 6 mil microstrip FR4, EQ Setting 0x07, Deterministic Jitter at PRBS-7 (27-1) pattern 0.12 0.20 UIP-P 5 Gbps (Note 5, 6) DJ4 Residual 40” of 6 mil microstrip FR4, EQ Setting 0x07, Deterministic Jitter at PRBS-7 (27-1) pattern 0.10 0.16 UIP-P 2.5 Gbps (Note 5, 6) RJ Random Jitter (Note 7, 8) 0.5 psrms 4 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Links: DS64EV100 |
Similar Part No. - DS64EV100_14 |
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Similar Description - DS64EV100_14 |
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