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DS92LX1621 Datasheet(PDF) 4 Page - Texas Instruments |
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DS92LX1621 Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 48 page  DS92LX1621, DS92LX1622 SNLS327I – MAY 2010 – REVISED JANUARY 2014 www.ti.com DS92LX1621 Serializer PIN DESCRIPTIONS (continued) Pin Name Pin No. I/O, Type Description SERIAL CONTROL BUS - I2C COMPATIBLE Clock line for the serial control bus communication SCL 4 Input/Output, Digital SCL requires an external pull-up resistor to VDDIO. Input/Output, Open Data line for the serial control bus communication SDA 5 Drain SDA requires an external pull-up resistor to VDDIO. I2C Mode Select Input, LVCMOS w/ M/S 8 M/S = L, Master (default); device generates and drives the SCL clock line pull down M/S = H, Slave; device accepts SCL clock input Continuous Address Decoder Input pin to select the Slave Device Address. CAD 6 Input, analog Input is connect to external resistor divider to programmable Device ID address (See Figure 29). CONTROL AND CONFIGURATION Power down Mode Input Pin. Input, LVCMOS w/ PDB = H, Transmitter is enabled and is ON. PDB 9 pull down PDB = L, Transmitter is in Sleep (Power Down). When the transmitter is in the SLEEP state, the PLL is shutdown, and IDD is minimized. Input, LVCMOS w/ RES 7 Reserved. This pin MUST be tied LOW. pull down Channel Link III INTERFACE DOUT+ 13 Input/Output, CML Non-inverting differential output, back-channel input. DOUT- 12 Input/Output, CML Inverting differential output, back-channel input. Power and Ground VDDPLL 10 Power, Analog PLL Power, 1.8V ±5% VDDT 11 Power, Analog Tx Analog Power, 1.8V ±5% VDDCML 14 Power, Analog LVDS & BC Dr Power, 1.8V ±5% VDDD 28 Power, Digital Digital Power, 1.8V ±5% VDDIO 25 Power, Digital Power for input stage, The single-ended inputs are powered from VDDIO. VSS DAP Ground, DAP DAP must be grounded. Connect to ground plane with at least 9 vias. 4 Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DS92LX1621 DS92LX1622 |
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