SCANSTA112

www.ti.com

SNLS161I – DECEMBER 2002 – REVISED APRIL 2013

SCANSTA112 7-Port Multidrop IEEE 1149.1 (JTAG) Multiplexer

Check for Samples: SCANSTA112

1

FEATURES

DESCRIPTION

The SCANSTA112 extends the IEEE Std. 1149.1 test

2

•

True IEEE 1149.1 Hierarchical and Multidrop

bus into a multidrop test bus environment. The

Addressable Capability

advantage of a multidrop approach over a single

•

The 8 Address Inputs Support up to 249

serial scan chain is improved test throughput and the

Unique Slot Addresses, an Interrogation

ability to remove a board from the system and retain

Address, Broadcast Address, and 4 Multi-Cast

test

access

to

the

remaining

modules.

Each

Group Addresses (Address 000000 is

SCANSTA112 supports up to 7 local IEEE1149.1

scan chains which can be accessed individually or

Reserved)

combined serially.

•

7 IEEE 1149.1-Compatible Configurable Local

Scan Ports

Addressing is accomplished by loading the instruction

register with a value matching that of the Slot inputs.

•

Backplane and inter-board testing can easily be

Interchangeable Slave Ports

accomplished by parking the local TAP Controllers in

•

Capable of Ignoring TRST of the Backplane

one of the stable TAP Controller states via a Park

Port when it Becomes the Slave.

instruction. The 32-bit TCK counter enables built in

•

Stitcher Mode Bypasses Level 1 and 2

self test operations to be performed on one port while

other scan chains are simultaneously tested.

Protocols

•

The STA112 has a unique feature in that the

Bypassed, Selected for Insertion into the Scan

backplane port and the LSP0 port are bidirectional.

They can be configured to alternatively act as the

Chain Individually, or Serially in Groups of

master or slave port so an alternate test master can

Two or Three

take control of the entire scan chain network from the

•

Transparent Mode can be Enabled with a

LSP0 port while the backplane port becomes a slave.

Single Instruction to Conveniently Buffer the

Backplane IEEE 1149.1 Pins to Those on a

Single Local Scan Port

•

General Purpose Local Port Pass Through Bits

are Useful for Delivering Write Pulses for Flash

Programming or Monitoring Device Status.

•

Known Power-Up State

•

TRST on all Local Scan Ports

•

32-bit TCK Counter

•

16-bit LFSR Signature Compactor

•

Local TAPs can Become TRI-STATE via the OE

Input to Allow an Alternate Test Master to Take

STATE Notification Output)

•

•

Supports Live Insertion/Withdrawal

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Copyright © 2002–2013, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.