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TLV320AIC3263 Datasheet(PDF) 11 Page - Texas Instruments |
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TLV320AIC3263 Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 62 page  TLV320AIC3263 www.ti.com SLAS923 – JUNE 2013 Electrical Characteristics, SAR ADC TA = 25°C; AVDD_18, AVDDx_18, HVDD_18, CPVDD_18, DVDD, IOVDDx = 1.8V; RECVDD_33 = 3.3V; SVDD, SPK_V, MICBIAS_VDD = 3.6V; fS (Audio) = 48kHz; Audio Word Length = 20 bits; Cext = 1μF on VREF_SAR and VREF_AUDIO pins; PLL disabled unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SAR ADC Inputs Analog Input voltage range 0 VREF_SAR V Input Input impedance IN1L/AUX1 or IN1R/AUX2 Selected 1 ÷ (f×CSAR_IN) (1) k Ω Input capacitance, CSAR_IN 25 pF Input leakage current 1 µA Battery VBAT Input voltage range 2.2 5.5 V Input VBAT (Battery measurement) VBAT Input impedance 5 k Ω selected(2) VBAT Input capacitance 25 pF VBAT Input leakage current 1 µA SAR ADC Conversion Resolution Programmable: 8-bit, 10-bit, 12-bit 8 12 Bits No missing codes 12-bit resolution 11 Bits IN1L/ Integral linearity ±1 LSB 12-bit resolution, SAR ADC clock = AUX1 Internal Oscillator Clock, Conversion Offset error clock = Internal Oscillator / 4, External ±1 LSB Reference = 1.8V(3) Gain error -0.09 % Noise DC voltage applied to IN1L/AUX1 = 1 V, ±1 LSB SAR ADC clock = Internal Oscillator Clock, Conversion clock = Internal Oscillator / 4, External Reference = 1.8V(4)(3) VBAT Accuracy 12-bit resolution, SAR ADC clock = 2 % Internal Oscillator Clock, Conversion Offset error ±2 LSB clock = Internal Oscillator / 4, Internal Gain error 1.5 % Reference = 1.25V Noise DC voltage applied to VBAT = 3.6 V, 12- ±0.5 LSB bit resolution, SAR ADC clock = Internal Oscillator Clock, Conversion clock = Internal Oscillator / 4, Internal Reference = 1.25V Conversion Rate Normal conversion operation 12-bit resolution, SAR ADC clock = 12 119 kHz MHz External Clock, Conversion clock = External Clock / 4, External Reference = 1.8V(3). With Fast SPI reading of data. High-speed conversion 8-bit resolution,SAR ADC clock = 12 250 kHz operation MHz External Clock, Internal Conversion clock = External Clock (Conversion accuracy is reduced.), External Reference = 1.8V(3). With Fast SPI reading of data. Voltage Reference - VREF_SAR Voltage range Internal VREF_SAR 1.25±0.05 V External VREF_SAR 1.25 AVDDx_18 V Reference Noise CM=0.9V, Cref = 1μF 46 μVRMS Decoupling Capacitor 1 μF (1) SAR input impedance is dependent on the sampling frequency (f designated in Hz), and the sampling capacitor is CSAR_IN = 25pF. (2) When VBAT is not being sampled/converted. When VBAT is being sampled, effective input impedance to GND is 5.24k Ω. (3) When utilizing External SAR reference, this external reference should be restricted VEXT_SAR_REF≤AVDD_18 and AVDD2_18. (4) Noise from external reference voltage is excluded from this measurement. Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: TLV320AIC3263 |
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