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DRV8837 Datasheet(PDF) 11 Page - Texas Instruments |
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DRV8837 Datasheet(HTML) 11 Page - Texas Instruments |
11 / 26 page DRV8837, DRV8838 www.ti.com SLVSBA4C – JUNE 2012 – REVISED FEBRUARY 2014 7.3 Feature Description 7.3.1 Bridge Control The DRV8837 is controlled using a PWM input interface, also called an IN/IN interface. Each output is controlled by a corresponding input pin. Table 1 shows the logic for the DRV8837 device: Table 1. DRV8837 Device Logic nSLEEP IN1 IN2 OUT1 OUT2 Function (DC Motor) 0 X X Z Z Coast 1 0 0 Z Z Coast 1 0 1 L H Reverse 1 1 0 H L Forward 1 1 1 L L Brake The DRV8838 is controlled using a PHASE/ENABLE interface. This interface uses one pin to control the H- bridge current direction, and one pin to enable or disable the H-bridge. Table 2 shows the logic for the DRV8838: Table 2. DRV8838 Device Logic nSLEEP PH EN OUT1 OUT2 Function (DC Motor) 0 X X Z Z Coast 1 X 0 L L Brake 1 1 1 L H Reverse 1 0 1 H L Forward 7.3.2 Sleep Mode If the nSLEEP pin is brought to a logic-low state, the DRV883x enters a low-power sleep mode. In this state, all unnecessary internal circuitry is powered down. 7.3.3 Power Supplies and Input Terminals The input pins may be driven within their recommended operating conditions with or without the VCC and/or VM power supplies present. No leakage current path will exist to the supply. There is a weak pulldown resistor (approximately 100 k Ω) to ground on each input pin. VCC and VM may be applied and removed in any order. When VCC is removed, the device will enter a low power state and draw very little current from VM. VCC and VM may be connected together if the supply voltage is between 1.8 and 7 V. The VM voltage supply does not have any undervoltage lockout protection (UVLO), so as long as VCC > 1.8 V; the internal device logic will remain active. This means that the VM pin voltage may drop to 0 V, however, the load may not be sufficiently driven at low VM voltages. 7.3.4 Protection Circuits The DRV883x is fully protected against VCC undervoltage, overcurrent, and overtemperature events. VCC Undervoltage Lockout: If at any time the voltage on the VCC pin falls below the undervoltage lockout threshold voltage, all FETs in the H-bridge will be disabled. Operation resumes when VCC rises above the UVLO threshold. Overcurrent Protection (OCP): An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this analog current limit persists for longer than tDEG, all FETs in the H-bridge will be disabled. Operation resumes automatically after tRETRY has elapsed. Overcurrent conditions will be detected on both the high-side and low-side devices. A short to VM, GND, or from OUT1 to OUT2 results in an overcurrent condition Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: DRV8837 DRV8838 |
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