30180903

LM3017

SNOSC66C – MARCH 2012 – REVISED MARCH 2013

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

CONNECTION DIAGRAM

10-PIN VQFN

TOP VIEW

PIN DESCRIPTIONS

PIN

DESCRIPTION

FUNCTION

NAME

NO.

Output of internal regulator powering low side NMOS driver. A minimum of 0.47µF

VCC

1

Driver supply voltage pin

must be connected from this pin to PGND for proper operation.

Low-side NMOS gate driver

DR

2

Output gate drive to low side NMOS gate.

output

Ground for power section. External power circuit reference. Should be connected

PGND

3

Power Ground

to AGND at a single point.

High side NMOS gate driver

VG

4

Output gate drive to high side NMOS gate.

output

This input provides for chip enable, and mode selection. See functional description

EN/MODE

5

Multi-function input pin

for details.

Negative input to error amplifier. Connect to feed-back resistor tap to regulate

FB

6

Feed-back input pin

output.

A resistor and capacitor combination connected to this pin provides frequency

COMP

7

Compensation pin

compensation for the regulator control loop.

AGND

8

Analog Ground

Ground for analog control circuitry. Reference point for all stated voltages.

ISEN

9

Current sense input

Current sense input, with respect to Vin, for all current limit functions.

Input supply to regulator. See applications section for recommendations on bypass

VIN

10

Power Supply input pin

capacitors on this pin.

2

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