LM5033

SNVS181A – MAY 2004 – REVISED MAY 2005

www.ti.com

FUNCTIONAL DESCRIPTION

The LM5033 High Voltage PWM controller contains all of the features needed to implement Push-Pull and Bridge

topologies, using voltage-mode control in a small 10 pin package. Features included are: startup regulator,

precision 2.5V reference output, current limit detection, alternating gate drivers, sync capability, thermal

shutdown, softstart, and remote shutdown. This high speed IC has total propagation delays <100 ns. These

features simplify the design of an open loop DC-DC converter, or a voltage controlled closed loop converter. The

Functional Block Diagram is shown in Figure 2.

High Voltage Start-Up Regulator (Pins 1, 4)

line voltages as high as 90V for normal operation, and can withstand transients to 100V. The regulator output at

under-voltage sensor (typically 9.5V), the under-voltage sensor resets, enabling the output drivers, although the

PWM duty cycle will initially be at zero. As the Softstart capacitor then charges up (described below) the output

above mentioned delay depends on the total system design and its start-up characteristics. The recommended

outputs are enabled, and the softstart sequence repeats.

internal regulator to shut off. The under-voltage sensor circuit will still function in this mode, requiring that the

be limited as to not exceed the regulator’s current limit, or the maximum power dissipation of the IC. An external

pins together and feeding the external bias voltage (10-15V) into that node.

A thermal shutdown protection will activate if the die temperature exceeds 165ºC, disabling the outputs (OUT1

Reference (Pin 2)

The Ref pin provides a reference voltage of 2.5V, ±2.4%. The pin is internally connected to an NMOS FET drain

at the buffer amplifier’s output, allowing it to sink, but not source current. An external pullup resistor is required.

Current into the pin must be limited to less than 20 mA to maintain regulation. See the graph in the Typical

Performance Characteristics.

During start-up if the pullup voltage is present before the reference amplifier establishes regulation, the voltage

on pin 2 must not exceed 5.5V. If this reference is not used the Ref pin can float or be connected to ground.

PWM Comparator (Pin 3), Duty Cycle and Deadtime

The PWM comparator compares an internal ramp signal (0 - 0.65V) with the loop error voltage derived from the

Comp pin (pin 3). The Comp voltage is typically set by an external error amplifier through an optocoupler for

closed loop applications. Internally, the voltage at the Comp pin passes through two level shifting diodes, and a

gain reducing 3:1 resistor divider. The output of the PWM comparator provides the pulse width information to the

output drivers (Out1 and Out2). This comparator is optimized for speed in order to achieve minimum discernable

Performance Characteristics. The maximum duty cycle for each output is limited to less than 50% due to the

forced deadtime. The typical deadtime between the falling edge of one gate driver output and the rising edge of

the other gate driver output is 135 ns, and does not vary with frequency. The maximum duty cycle for each

output can be calculated from:

8

Submit Documentation Feedback

Copyright © 2004–2005, Texas Instruments Incorporated

Product Folder Links: LM5033