LM5060

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SNVS628E – OCTOBER 2009 – REVISED JANUARY 2012

Pin Descriptions (continued)

Pin

Name

Description

Applications Information

No.

The UVLO pin is used as an input Under-Voltage Lock-Out by connecting this pin to a resistor

divider between input supply voltage and ground. The UVLO comparator is activated when EN is

Under-Voltage Lock-

4

UVLO

high. A voltage greater than typically 1.6V at the UVLO pin will release the pull down devices on

Out Comparator Input

the GATE pin and allow the output to gradually rise. A constant current sink (5.5 µA typical) is

provided to guarantee the UVLO pin is low in an open circuit condition.

A voltage less than 0.8V on the EN pin switches the LM5060 to a low current shutdown state. A

voltage greater than 2.0V on the EN pin enables the internal bias circuitry and the UVLO

5

EN

Enable Input

comparator. The GATE pin pull-up bias is enabled when both EN and UVLO are in the high

state. A constant current sink (6 µA typical) is provided to guarantee the EN pin is low in an open

circuit condition.

6

GND

Circuit ground

7

TIMER

Timing capacitor

pin exceeds the 2.0V threshold condition, the LM5060 will latch off the MOSFET and remain off

until either the EN, UVLO or VIN (POR) input is toggled low and then high.

8

nPGD

Fault Status

exceeds the SENSE pin voltage, the nPGD indicator is active (low = no fault).

9

OUT

Output VoltageSense

conditions.

Connect to the external MOSFET’s gate. A charge-pump driven constant current source (24 µA

typical) charges the GATE pin. An internal zener clamps the GATE pin at typically 16.8V above

10

GATE

Gate drive output

the OUT pin. The

ΔV/Δt of the output voltage can be reduced by connecting a capacitor from the

GATE pin to ground.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Absolute Maximum Ratings

(1)

(2) (3)

-0.3V to 75V

-0.3V to 75V

-0.3V to 75V

-0.3V to 75V

nPGD, OVP to GND

-0.3V to 75V

TIMER to GND

-0.3V to 7V

2 kV

Storage Temperature

−65°C to + 150°C

260°C

Junction Temperature

150°C

(1)

Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including in-operability and degradation of

device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or

other conditions beyond those indicated in the Recommended Operating Conditions is not implied. Operating Range conditions indicate

the conditions at which the device is functional and the device should not be operated beyond such conditions. For guaranteed

specifications and conditions, see the Electrical Characteristics table.

(2)

The GATE pin voltage is typically 12V above the VIN pin when the LM5060 is enabled. Therefore, the Absolute Maximum Rating for VIN

(75V) applies only when the LM5060 is disabled, or for a momentary surge to that voltage since the Absolute Maximum Rating for the

GATE pin is also 75V.

(3)

The minimum voltage of -1V is allowed if the current is limited to below -25 mA. Also it is assumed that the negative voltage on the pins

only occur during reverse battery condition when a positive supply voltage (Vin) is not applied.

(4)

The minimum voltage of -25V is allowed if the current is limited to below -25 mA. Also it is assumed that the negative voltage on the

pins only occur during reverse battery condition when a positive supply voltage (VIN) is not applied.

(5)

The Human Body Model (HBM) is a 100 pF capacitor discharged through a 1.5 k

Ω resistor into each pin. Applicable standard is JESD-

22–A114–C.

(6)

Soldering process must comply with National Semiconductor's Reflow Temperature Profile specifications. Reflow temperature profiles

are different for lead-free and non-lead-free packages. Refer to the Packaging Data Book available from National Semiconductor, or :

www.national.com/analog/packaging

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