© 2003 Fairchild Semiconductor Corporation

DS500588

www.fairchildsemi.com

September 2001

Revised August 2003

FIN1048

3.3V LVDS 4-Bit Flow-Through

High Speed Differential Receiver

General Description

This quad receiver is designed for high speed interconnect

utilizing Low Voltage Differential Signaling (LVDS) technol-

ogy. The receiver translates LVDS levels, with a typical dif-

ferential input threshold of 100mV, to LVTTL signal levels.

LVDS provides low EMI at ultra low power dissipation even

at high frequencies. This device is ideal for high speed

transfer of clock and data.

The FIN1048 can be paired with its companion driver, the

FIN1047, or any other LVDS driver.

Features

s Greater than 400Mbs data rate

s Flow-through pinout simplifies PCB layout

s 3.3V power supply operation

s 0.4ns maximum differential pulse skew

s 2.5ns maximum propagation delay

s Low power dissipation

s Power-Off protection

s Fail safe protection for open-circuit, shorted and termi-

nated conditions

s Meets or exceeds the TIA/EIA-644 LVDS standard

s Pin compatible with equivalent RS-422 and LVPECL

devices

s 16-Lead SOIC and TSSOP packages save space

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Pin Descriptions

Function Table

H

= HIGH Logic Level

L

= LOW Logic Level

X

= Don’t Care

Z

= High Impedance

Fail Safe

= Open, Shorted, Terminated

Order Number

Package Number

Package Description

FIN1048M

M16A

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

FIN1048MTC

MTC16

16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Pin Name

Description

Non-Inverting LVDS Inputs

Inverting LVDS Inputs

EN

Driver Enable Pin

EN

Inverting Driver Enable Pin

Power Supply

GND

Ground

Inputs

Outputs

EN

EN

HL or Open

H

L

H

HL or Open

L

H

L

H

L or Open Fail Safe Condition

H

XH

X

X

Z

L or Open

X

X

X

Z