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X5323PIZ-4.5A Datasheet(PDF) 8 Page - Intersil Corporation |
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X5323PIZ-4.5A Datasheet(HTML) 8 Page - Intersil Corporation |
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8 / 20 page  8 FN8131.2 June 30, 2008 . The watchdog timer bits, WD0 and WD1, select the watchdog time out period. These nonvolatile bits are programmed with the WRSR instruction. The FLAG bit shows the status of a volatile latch that can be set and reset by the system using the SFLB and RFLB instructions. The flag bit is automatically reset upon power-up. This flag can be used by the system to determine whether a reset occurs as a result of a watchdog time out or power failure. Note: The Watch Dog Timer is shipped disabled. (WD1 = 1, WD0 = 1. The factory default for Memory Block Protection is ‘None’. (BL1 = 0, BL0 = 0). The nonvolatile WPEN bit is programmed using the WRSR instruction. This bit works in conjunction with the WP pin to provide an in-circuit programmable ROM function (Table 2). WP is LOW and WPEN bit programmed HIGH disables all status register write operations. In Circuit Programmable ROM Mode This mechanism protects the block lock and watchdog bits from inadvertent corruption. In the locked state (programmable ROM mode) the WP pin is LOW and the nonvolatile bit WPEN is “1”. This mode disables nonvolatile writes to the device’s status register. Setting the WP pin LOW while WPEN is a “1” while an internal write cycle to the status register is in progress will not stop this write operation, but the operation disables subsequent write attempts to the status register. When WP is HIGH, all functions, including nonvolatile writes to the status register operate normally. Setting the WPEN bit in the status register to “0” blocks the WP pin function, allowing writes to the status register when WP is HIGH or LOW. Setting the WPEN bit to “1” while the WP pin is LOW activates the programmable ROM mode, thus requiring a change in the WP pin prior to subsequent status register changes. This allows manufacturing to install the device in a system with WP pin grounded and still be able to program the status register. Manufacturing can then load configuration data, manufacturing time and other parameters into the EEPROM, then set the portion of memory to be protected by setting the block lock bits, and finally set the “OTP mode” by setting the WPEN bit. Data changes now require a hardware change. Read Sequence When reading from the EEPROM memory array, CS is first pulled low to select the device. The 8-bit READ instruction is transmitted to the device, followed by the 16-bit address. After the READ opcode and address are sent, the data stored in the memory at the selected address is shifted out on the SO line. The data stored in memory at the next address can be read sequentially by continuing to provide clock pulses. The address is automatically incremented to the next higher address after each byte of data is shifted out. STATUS REGISTER BITS ARRAY ADDRESSES PROTECTED BL1 BL0 X5323/X5325 0 0 None (factory default) 0 1 $0C00 to $0FFF 1 0 $0800 to $0FFF 1 1 $0000 to $0FFF STATUS REGISTER BITS WATCHDOG TIME-OUT (TYPICAL) WD1 WD0 0 0 1.4s 0 1 600ms 1 0 200ms 1 1 disabled (factory default) 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 7 6 543 21 0 DATA OUT CS SCK SI SO MSB HIGH IMPEDANCE INSTRUCTION 16-BIT ADDRESS 15 14 13 3 2 1 0 FIGURE 5. READ EEPROM ARRAY SEQUENCE X5323, X5325 |
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