 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
X5323P-2.7A Datasheet(PDF) 9 Page - Intersil Corporation |
|
||||||||||||||||||||||||||||||
X5323P-2.7A Datasheet(HTML) 9 Page - Intersil Corporation |
|
|
9 / 20 page  9 FN8131.2 June 30, 2008 When the highest address is reached, the address counter rolls over to address $0000 allowing the read cycle to be continued indefinitely. The read operation is terminated by taking CS high. Refer to the read EEPROM Array Sequence (Figure 1). To read the status register, the CS line is first pulled low to select the device followed by the 8-bit RDSR instruction. After the RDSR opcode is sent, the contents of the status register are shifted out on the SO line. Refer to the read status register sequence (Figure 2). Write Sequence Prior to any attempt to write data into the device, the “Write Enable” Latch (WEL) must first be set by issuing the WREN instruction (Figure 3). CS is first taken LOW, then the WREN instruction is clocked into the device. After all eight bits of the instruction are transmitted, CS must then be taken HIGH. If the user continues the write operation without taking CS HIGH after issuing the WREN instruction, the write operation will be ignored. To write data to the EEPROM memory array, the user then issues the WRITE instruction followed by the 16-bit address and then the data to be written. Any unused address bits are specified to be “0’s”. The WRITE operation minimally takes 32 clocks. CS must go low and remain low for the duration of the operation. If the address counter reaches the end of a page and the clock continues, the counter will roll back to the first address of the page and overwrite any data that may have been previously written. Note: When writing more than one page, you must wait one write cycle (10ms typical) when going from one page to another. This is required for the internal nonvolatile memory to be programmed correctly. For the page write operation (byte or page write) to be completed, CS can only be brought HIGH after bit 0 of the last data byte to be written is clocked in. If it is brought HIGH at any other time, the write operation will not be completed (Figure 4). To write to the status register, the WRSR instruction is followed by the data to be written (Figure 5). Data bits 0 and 1 must be “0”. While the write is in progress following a status register or EEPROM Sequence, the status register may be read to check the WIP bit. During this time the WIP bit will be high. Operational Notes The device powers-up in the following state: • The device is in the low power standby state. • A HIGH to LOW transition on CS is required to enter an active state and receive an instruction. • SO pin is high impedance. • The write enable latch is reset. • The flag bit is reset. • Reset signal is active for tPURST. Data Protection The following circuitry has been included to prevent inadvertent writes: • A WREN instruction must be issued to set the write enable latch. •CS must come HIGH at the proper clock count in order to start a nonvolatile write cycle. 012 345 678 9 10 11 12 13 14 7 654 321 0 DATA OUT CS SCK SI SO MSB HIGH IMPEDANCE INSTRUCTION FIGURE 6. READ STATUS REGISTER SEQUENCE X5323, X5325 |
Similar Part No. - X5323P-2.7A |
|
Similar Description - X5323P-2.7A |
|
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
