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MB15C103PV1 Datasheet(PDF) 6 Page - Fujitsu Component Limited.

Part # MB15C103PV1
Description  IF Band PLL Frequency Synthesizer
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Manufacturer  FUJITSU [Fujitsu Component Limited.]
Direct Link  http://edevice.fujitsu.com/fmd/en/index.html
Logo FUJITSU - Fujitsu Component Limited.

MB15C103PV1 Datasheet(HTML) 6 Page - Fujitsu Component Limited.

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MB15C103
s FUNCTIONAL DESCRIPTIONS
Two different frequencies can be selected by DIV input “H” or “L”.
The divide ratios are calculated using the following equation:
fVCO = {(P x N) + A} x fOSC
÷ R (A < N)
s PHASE DETECTOR TIME CHART
Note: • Phase error detection range: –2
π to +2π
• Pulses on Do output signal during locked state are output to prevent dead zone.
• LD output becomes low when phase is tWU or more. LD output becomes high when phase error is tWL or
less and continues to be so for three cycles or more.
•tWU and tWL depend on OSCIN input frequency.
tWU > 8/fosc (s) (e. g.tWU > 625.0ns, fosc = 12.8 MHz)
tWL < 16/fosc (s) (e. g. tWL < 1250.0ns, fosc = 12.8 MHz)
Symbol
Description
DIV = “H”
DIV = “L”
fvco
Output frequency of external VCO
178.00 MHz
129.55 MHz
fosc
Reference oscillation frequency
12.8 MHz
12.8 MHz
N
Divide ratio of the main counter
27
161
A
Divide ratio of the swallow counter
13
15
P
Preset divide ratio of dual modulus
prescaler
16/17
16/17
R
Divide ratio of the reference counter
32 (fr = 400 kHz)
256 (fr = 50 kHz)
fr
fp
LD
DO
High impedance
tWL
tWU


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