MB15F03PFV datasheet(8/22 Pages) FUJITSU

Part #	MB15F03PFV

Description	Dual Serial Input PLL Frequency Synthesizer

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Manufacturer	FUJITSU [Fujitsu Component Limited.]

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8

MB15F03

Table2. Binary 14-bit Programmable Reference Counter Data Setting

Note:

• Divide ratio less than 5 is prohibited.

Table.3 Test Purpose Bit Setting

Divide

ratio

(R)

R

14

R

13

R

12

R

11

R

10

R

9

R

8

R

7

R

6

R

5

R

4

R

3

R

2

R

1

5

0

0000000000101

6

0

0000000000110

⋅

⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅

16383

1

T

1

T

2

LD/fout pin state

L

Outputs frIF.

H

L

Outputs frRF.

L

H

Outputs fpIF.

H

Outputs fpRF.

Programmable Counter

C

N

1

2

L

D

3

F

C

4

A

1

5

A

2

6

A

3

7

A

4

8

A

5

9

A

6

10

A

7

11

N

1

12

N

2

13

N

3

14

N

4

15

N

5

16

N

6

17

LS

MS

Data

C

N

2

S

W

18

CNT1, 2

: Control bit

[Table. 1]

N1 to N14

: Divide ratio setting bits for the programmable counter (5 to 2,047)

[Table. 4]

A1 to A7

: Divide ratio setting bits for the swallow counter (0 to 127)

[Table. 5]

SW

: Divide ratio setting bit for the prescaler

[Table. 6]

(16/17 or 32/33 for the IF-PLL, 64/65 OR 128/129 for the RF-PLL)

FC

: Phase control bit for the phase detector

[Table. 7]

LDS

: LD/fout signal select bit

[Table. 8]

NOTE: Data input with MSB ﬁrst.

N

7

N

8

19

N

9

20

N

10

21

N

11

22

23

S

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