MB15F78SP

2

(Continued)

• Dual modulus prescaler : 2550 MHz prescaler (32/33 or 64/65 )/1200 MHz prescaler (16/17 or 32/33)

• 23-bit shift register

• Serial input binary 14-bit programmable reference divider : R = 3 to 16,383

• Serial input programmable divider consisting of:

- Binary 7-bit swallow counter : 0 to 127

- Binary 11-bit programmable counter: 3 to 2,047

• Built-in high-speed tuning, low-noise phase comparator, current-switching type constant current circuit

• On–chip phase control for phase comparator

• Built-in digital locking detector circuit to detect PLL locking and unlocking

• Operating temperature : Ta = –40 to +85

°C

• Sireal data format compatible with MB15F08SL

s

s

s

s PIN ASSIGNMENTS

GND

LD/fout

Clock

Data

LE

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

GND

1

2

3

4

5

6

7

8

9 10

11

12

13

14

15

16

19 18 17

20

LE

LD/fout

Data

Clock

(TSSOP-20)

TOP VIEW

(BCC-20)

TOP VIEW

(FPT-20P-M06)

(LCC-20P-M04)