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TRP3FE0L1C00000G Datasheet(PDF) 4 Page - OPLINK Communications Inc.

Part # TRP3FE0L1C00000G
Description  Fast Ethernet SFP Multimode Transceivers
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Manufacturer  OPLINK [OPLINK Communications Inc.]
Direct Link  http://www.oplink.com
Logo OPLINK - OPLINK Communications Inc.

TRP3FE0L1C00000G Datasheet(HTML) 4 Page - OPLINK Communications Inc.

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Oplink Communications, Inc.
RevA-PN.2009.06.25
18
19
3
TX DATA IN+
15
1µH coil or ferrite bead
(<0.2Ω series resistance)
0.1
TX DATA IN-
TX Disable
16
0.1
+10
50Ω line
50Ω line
50Ω line
50Ω line
1, 9, 10, 11, 14, 17, 20
0.1
+ 10
(100 to ground internally)
to 50Ω load
Vcc
3.3V
RX DATA OUT+
13
12
RX DATA OUT-
5
4
6
MOD_DEF(0)
MOD_DEF(1)
MOD_DEF(2)
LOS
to 50Ω load
8
R
RR
Vcc
3.3V
+10
Example of SFP host board schematic
Figure 1 - Trade-off
curves in FDDI PMD
document
TRXNFEMM
Application Notes
Electrical Interface: Electrical interface: All signal interfaces are
compliant with the SFP MSA specification. The high speed DATA
interface is differential AC-coupled internally and can be directly
connected to a 3.3V SERDES IC. All low speed control and sense
output signals are open collector TTL compatible and should be
pulled up with a 4.7 - 10kΩ resistor on the host board.
Loss of Signal (LOS): The Loss of Signal circuit monitors the level
of the incoming optical signal and generates a logic HIGH when an
insufficient photocurrent is produced.
TX Fault: Per SFP MSA, pin 2 is TX Fault. This transceiver is LED based
and does not support TX Fault. Pin 2 is internally connected to
transmitter circuit ground (TX GND) to indicate normal operation.
TX Disable:When theTX Disable pin is at logic HIGH, the transmitter
optical output is disabled (less than -45dBm).
Serial Identification: The module definition of SFP is indicated by
the three module definition pins, MOD_DEF(0), MOD_DEF(1) and
MOD_DEF(2). Upon power up, MOD_DEF(1:2) appear as NC (no
connection), and MOD_DEF(0) is TTL LOW. When the host system
detects this condition, it activates the serial protocol (standard two-
wire I2C serial interface) and generates the serial clock signal (SCL).
The negative edge clocks data from the SFP EEPROM.
The serial data signal (SDA) is for serial data transfer. The host uses
SDA in conjunction with SCL to mark the start and end of serial
protocol activation.
The data transfer protocol and the details of the mandatory and
vendor specific data structures are defined in the SFP MSA.
Power Supply and Grounding: The power supply line should be
well-filtered. All 0.1μF power supply bypass capacitors should be as
close to the transceiver module as possible.
4
TRXNFEMM
R: 4.7 to 10kΩ
100
120
140
160
180
200
1280
1300
1320
1340
1360
1380
SOURCE CENTER WAVELENGTH (nm)
1.5
2.0
2.5
3.0
3.5
3.0
3.5
Source rise & fall time (ns)


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