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TRPEG1KZXC000L0G Datasheet(PDF) 4 Page - OPLINK Communications Inc. |
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TRPEG1KZXC000L0G Datasheet(HTML) 4 Page - OPLINK Communications Inc. |
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4 / 6 page  4 TRPEG1-G MR CWDM Oplink Communications, Inc S0143, Rev.03. (web) 2013-05-17 Application Notes Electrical interface: All signal interfaces are compliant with the SFP MSA specification. The high speed DATA interface is differential AC-coupled internally with 1μF and can be directly connected to a 3.3V SERDES IC. All low speed control and sense output signals are open collector TTL compatible and should be pulled up with a 4.7 - 10kΩ resistor on the host board. Loss of Signal (LOS): The Loss of Signal circuit monitors the level of the incoming optical signal and generates a logic HIGH when an insufficient photocurrent is produced. TX_Fault: The output indicates LOW when the transmitter is operating normally, and HIGH with a laser fault including laser end-of-life. TX Fault is an open collector/drain output that should be pulled up with a 4.7 - 10kΩ resistor on the host board. TX Fault is latched per SFP MSA. TX_Disable: When the TX Disable pin is at logic HIGH, the transmitter optical output is disabled (less than -45dBm). Serial Identification and Monitoring: The module definition of SFP is indicated by the three module definition pins, MOD_DEF(0), MOD_DEF(1) and MOD_DEF(2). Upon power up, MOD_DEF(1:2) appear as NC (no connection), and MOD_DEF(0) is TTL LOW. When the host system detects this condition, it activates the serial protocol (standard two-wire I2C serial interface) and generates the serial clock signal (SCL). The positive edge clocks data into the EEPROM segments of the SFP that are not write protected, and the negative edge clocks data from the SFP. The serial data signal (SDA) is for serial data transfer. The host uses SDA in conjunction with SCL to mark the startand end of serial protocol activation. The supported monitoring functions are internal temperature, supply voltage, bias current, transmitter power, average receiver signal, all alarms and warnings and software monitoring of TX Fault/LOS. The device is internally calibrated. The data transfer protocol and the details of the mandatory and vendor specific data structures are defined in the SFPMSA, and SFF-8472, Rev. 9.4. Power supply and grounding: The power supply line should be well-filtered. All 0.1μF power supply bypass capacitors should be as close to the transceiver module as possible. TX DATA IN+ 1H coil or ferrite bead µ (<0.2 Ω series resistance) 0.1 TX DATA IN- TX Disable 0.1 + 10 0.1 + 10 to 50 Ωload 3.3V RX DATA OUT+ RX DATA OUT- MOD_DEF(0) MOD_DEF(1) MOD_DEF(2) LOS to 50Ω load TX Fault Vcc 3.3V Vcc 50Ω line 50Ω line 50Ω line 50Ω line R R R R R 8 5 4 6 2 18 19 3 15 16 13 12 1, 9,10,11,14,17,20 Example of SFP host board schematic SFP R: 4.7 to 10kΩ CAP Values in µF |
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