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AFE4490 Datasheet(PDF) 5 Page - Texas Instruments |
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AFE4490 Datasheet(HTML) 5 Page - Texas Instruments |
5 / 96 page AFE4490 www.ti.com SBAS602G – DECEMBER 2012 – REVISED JUNE 2014 • Added Figure 24 ................................................................................................................................................................... 20 • Deleted Figure 23, Noise-Free Bits vs PLETH Current (BW = 5 Hz, PRF = 5000 Hz)........................................................ 20 • Added Figure 24 ................................................................................................................................................................... 21 • Deleted Figure 29, Noise-Free Bits vs PLETH Current (BW = 20 Hz, PRF = 5000 Hz)...................................................... 21 • Added Figure 38 through Figure 41 ..................................................................................................................................... 22 • Added Figure 49 to Figure 53............................................................................................................................................... 24 • Changed gain setting range in Receiver Front-End section................................................................................................. 28 • Changed corresponding register column description in rows t24, t26, and t28 in Table 2 ...................................................... 36 • Changed description of LED Power Reduction During Periods of Inactivity section ........................................................... 42 • Added text reference for Figure 64 in ADC Operation and Averaging Module section........................................................ 43 • Changed last paragraph of AFE Analog Output Mode (ADC Bypass Mode) section .......................................................... 48 • Updated Figure 76 ................................................................................................................................................................ 48 • Updated Figure 77 ................................................................................................................................................................ 49 • Changed LED2CONVEND register name in Table 4 ........................................................................................................... 55 • Changed RESERVED1 and RESERVED2 register descriptions in Table 4 ........................................................................ 57 • Changed description of bits D[15:0] in LED2STC register ................................................................................................... 58 • Changed description of bits D[15:0] in LED2ENDC, LED2LEDSTC, and LED2LEDENDC registers.................................. 59 • Changed description of bits D[15:0] in ALED2STC, ALED2ENDC, and LED1STC registers .............................................. 60 • Changed description of bits D[15:0] in LED1ENDC, LED1LEDSTC, and LED1LEDENDC registers.................................. 61 • Changed description of bits D[15:0] in ALED1STC, ALED1ENDC, and LED2CONVST registers ...................................... 62 • Changed description of bits D[15:0] in ALED2CONVST and ALED2CONVEND registers.................................................. 63 • Changed description of bits D[15:0] in LED1CONVST, LED1CONVEND, and ALED1CONVST registers ......................... 64 • Changed description of bits D[15:0] in ALED1CONVEND register ...................................................................................... 65 • Changed RESET to RESET in ADCRSTSTCT0 and ADCRSTENDCT0 registers.............................................................. 65 • Changed RESET to RESET in ADCRSTSTCT1, ADCRSTENDCT1, and ADCRSTSTCT2 registers ................................ 66 • Changed RESET to RESET in ADCRSTENDCT2, ADCRSTSTCT3, and ADCRSTENDCT3 registers ............................. 67 • Added footnote to Table 6 .................................................................................................................................................... 71 • Changed bits D18 and D17 names in CONTROL2 bit register............................................................................................ 72 • Added note to description of bits D[18:17] in CONTROL2 register...................................................................................... 72 • Changed RESERVED1 and RESERVED2 registers............................................................................................................ 74 Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: AFE4490 |
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