MB86604LPFV datasheet(6/56 Pages) FUJITSU

Part #	MB86604LPFV

Description	SCSI-II Protocol Controller (with single-ended driver/receiver)

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Manufacturer	FUJITSU [Fujitsu Component Limited.]

Direct Link	http://edevice.fujitsu.com/fmd/en/index.html

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6

MB86604L

(Continued)

* : The pin symbols in parenthesis are the ones when the MODE input is “L”.

3.

DMA Interface

(Continued)

number

Symbol*

Pin name

I/O

Function

100

BHE

(UDS)

Bus high

enable

(strobe)

I

In the 80-series mode, this pin is used for input of the bus high

enable signal (BHE) output from the MPU when the upper byte of

the data bus is valid. The BHE pin is an active-low. In the 68-

series mode, this pin functions as the upper data strobe signal

input pin (UDS) output from the MPU when the upper byte of the

data bus is valid. The UDS pin is also an active-low.

7INT

(INT)

Interrupt

request

O

The INT and INT pins are the interrupt request signal output. The

INT pins is used for the 80-series mode (an active-high pin), and

the INT signal is used for the 68-series mode (an active-low pin).

8

MODE

Mode

I

This input pin is used to select the type of the MPU and DMA

buses. In the 80-series mode, a high level is input. In the 68-

series mode, a low level is input.

number

Symbol*

Pin name

I/O

Function

52

DREQ

DMA request

O

This is an output pin of DMA transfer request signal to the DMA

controller. The data transfer between the SPC and memory via

the DMA bus is requested. This pin is an active-high.

51

DACK

DMA

acknowledge

I

This is a DMA acknowledge signal input pin output from the

DMA controller that enables the DMA transfer. This pin is an

active-low. When this pin is an active state, the DMA cycle (read/

write) is valid.

48, 47, 46,

45, 44, 43,

42, 41

DMD15

to

DMD8

DMA data 15

to

DMA data 8

I/O

These pins are the input/output pins of the upper byte and parity

bit of the DMA data bus. When the signal input to the CS1 pin

(pin 80) is valid, these pins are connected directly to the MPU

data bus.

49

UDMDP

Upper DMA

data parity

39, 38, 37,

36, 35, 34,

33, 32

DMD7

to

DMD0

DMA data 7

to

DMA data 0

I/O

These pins are the input/output pins of the lower byte and parity

bit of the DMA data bus. When the CS1 (pin 80) input is valid,

these pins are connected directly to the MPU data bus.

31

LDMDP

Lower DMA

data parity

27

IORD

(DMR/W)

I/O read

(DMA read/

write)

I

In the 80-series mode, this pin (IORD or RD) is used for the input

pin to output the data from the SPC to the DMA bus. This is an

active-low pin. In the 68-series mode, this pin functions as a

control signal input pin (DMR/W) to input/output the data to the

SPC by the DMA controller. In the output operation, this pin is on

the high-state (active-high state). In the input operation, this pin

is on the low-state (active-low state).

26

IOWR

(DMLDS)

I/O write

(DMA lower

data strobe)

I

In the 80-series mode, this (IOWR or WR) is used for the input

pin to input the DMA bus data to the SPC. In the 68-series mode,

this pin functions as a DMA lower data strobe input (DMLDS)

that DMA controller outputs when the lower byte of the DMA bus

data is valid. Both IOWR and DMLDS pins are an active-low.

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