MB86606APMT2 datasheet(10/64 Pages) FUJITSU

Part #	MB86606APMT2

Description	FAST-20 SCSI Protocol Controller

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Manufacturer	FUJITSU [Fujitsu Component Limited.]

Direct Link	http://edevice.fujitsu.com/fmd/en/index.html

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10

MB86606A

2. 16-Bit Bus Mode-MPU Interface

Pin no.

Pin name

I/O

Function

48

CS0

I

This is used to input signals for the MPU to select the SPC

as the I/O device.

47

CS1

I

This is used to input select signals (external circuit select

signals) for the MPU to input and output the DMA data bus

data via the SPC.

19, 20, 22 to 24, 26 to 28

17

D15 to D8

UDP

I/O

Upper byte and parity of data bus

When CS0 input valid: I/O ports for internal registers in SPC

When CS1 input valid: I/O ports for DMA bus data

29, 32 to 34, 36 to 39

41

D7 to D0

LDP

I/O

Lower byte and parity of data bus

When CS0 input valid: I/O ports for internal registers in SPC

When CS1 input valid: I/O ports for DMA bus data

51, 52, 55 to 57

A4 to A0

IU

These are used to input addresses for selecting the Internal

registers.

46

RD (R/W)I

In 80-series mode: This is used to input the read strobe

signal for reading data from the SPC to

the MPU.

In 68-series mode: This is used to input the R/W control

signal for reading and writing data from

the MPU to the SPC.

44

WR (LDS)I

In 80-series mode: This is used to input the write strobe

signal for writing data from the MPU to

the SPC.

In 68-series mode: This is used to input the LDS signal

output by the MPU when the lower byte

of the data bus is valid.

42

BHE (UDS)I

In 80-series mode: This is used to input the BHE signal

output by the MPU when the upper byte

of the data bus is valid.

In 68-series mode: This is used to input the UDS signal

output by the MPU when the upper byte

of the data bus is valid.

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MB86606APMT2 Datasheet(PDF) 10 Page - Fujitsu Component Limited.

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