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MB86967PFV Datasheet(PDF) 9 Page - Fujitsu Component Limited. |
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MB86967PFV Datasheet(HTML) 9 Page - Fujitsu Component Limited. |
9 / 129 page 9 MB86967 (Continued) Pin no. Symbol Pin name I/O Function 69 74 75 92 IREQ1/IOSEL0 IREQ2/IOSEL1 IREQ3/IOSEL2 IREQ0 INTERRUPT REQUEST 0 to 3 (Active High) IU/O Jumperless Mode These pins are used for output of IR signals. One of IREQ0 to IREQ3 is selected by configuration data in EEPROM. I/O ADDRESS SELECT Jumper Mode These pins are used to select the I/O base addresses to which the LAN controller is allocated. 83 DMACK DMA ACKNOWLEDGE I This pin is used for input of DMAC acknowledge signals indicating that the DMAC is ready to transmit and receive data to and from buffer memory. 3 IOCHRDY I/O CHANNEL READY (Active Low, open-drain output) OD This pin is used for output of signals indicating READY for handshaking with the host system. 84 IOCS16 I/O CHANNEL SELECT 16 (Active Low, open-drain output) OD This pin is used for output of signals indicating that data transfer is made in a 16-bit I/O access cycle. 93 ENHB ENABLE DATA HIGH (Active Low) O This pin is used for output of enable signals for an external upper system data bus transceiver. 95 ENLB ENABLE DATA LOW (Active Low) O This pin is used for output of enable signals for an external lower system data bus transceiver. 99 EEPSK SHIFT CLOCK O This pin is used for output of EEPROM shift clock pulses. 97 EEPDI DATA IN O This pin is connected to DATA IN pin of EEPROM. 96 EEPDO DATA OUT IU This pin is connected to DATA OUT pin of EEPROM. 98 EECS EEPROM CHIP SELECT (Active High) O This pin is used for output of EEPROM chip select signals. IOSEL2 IOSEL1 IOSEL0 I/O Base Address 00 0 260H to 27FH 00 1 280H to 29FH 01 0 2A0H to 2BFH 01 1 240H to 25FH 10 0 340H to 35FH 10 1 320H to 33FH 11 0 380H to 39FH 11 1 300H to 31FH |
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