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MB88101APFV Datasheet(PDF) 5 Page - Fujitsu Component Limited. |
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MB88101APFV Datasheet(HTML) 5 Page - Fujitsu Component Limited. |
5 / 18 page 5 MB88101A s FUNCTIONAL DESCRIPTION 1. Mode 1 This mode sets the DO pin to “L” and stops conversion upon completion of conversion of 12 bits. To restart conversion, set CS to “H” once then to “L”. In this mode, converted data is output from the MSB. • Timing diagram 2. Mode 2 This mode continues conversion until CS becomes “H” after it becomes “L”. Converted data is output from the LSB, with the first piece of converted data output 20 clock cycles after CS becomes “L”. Changing the channel select pin settings before starting sampling of one analog input allows another to be converted. • Timing diagram CLK CS MOD0, 1 C0, C1 DO Bit Trial SAMP B11 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Sampling Sampling 12345678910 11 12 13 14 15 16 1 2 Hi-z Hi-z Hi-z Hi-z CS MOD0, 1 MOD0, 1 Mode 2 C0, C1 AN0 AN2 AN1 CLK DO Bit Trial SAMP Hi-z Hi-z Hi-z Hi-z 16CLK MSB (AN0) ⇒ LSB MSB (AN2) ⇒ LSB LSB (AN0) ⇒ MSB LSB (AN2) ⇒ MSB MSB (AN1) ⇒ LSB |
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