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TSB43AB22

SLLA208 – JUNE 2006

Integrated 1394a-2000 OHCI PHY/Link-Layer Controller

•

PHY-Link logic performs system initialization

and arbitration functions

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Fully compliant with provisions of IEEE Std

•

PHY-Link encode and decode functions

and IEEE Std 1394a-2000

included for data-strobe bit level encoding

•

Fully interoperable with FireWire and i.LINK

•

PHY-Link incoming data resynchronized to

implementations of IEEE Std 1394

local clock

•

Compliant with Intel Mobile Power Guideline

•

Low-cost 24.576-MHz crystal provides

2000

transmit and receive data at 100M bits/s,

200M bits/s, and 400M bits/s

•

Full IEEE Std 1394a-2000 support includes:

connection debounce, arbitrated short reset,

•

Node power class information signaling for

multispeed concatenation, arbitration

system power management

acceleration, fly-by concatenation, and port

•

Serial ROM interface supports 2-wire serial

disable/suspend/resume

EEPROM devices

•

Power-down features to conserve energy in

•

Two general-purpose I/Os

battery-powered applications include:

•

Register bits give software control of

automatic device power down during

contender bit, power class bits, link active

suspend, PCI power management for

control bit, and IEEE Std 1394a-2000 features

link-layer, and inactive ports powered down

•

Fabricated in advanced low-power CMOS

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Ultralow-power sleep mode

process

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Two IEEE Std 1394a-2000 fully compliant

•

PCI and CardBus register support

cable ports at 100M bits/s, 200M bits/s, and

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Isochronous receive dual-buffer mode

400M bits/s

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Out-of-order pipelining for asynchronous

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Cable ports monitor line conditions for active

transmit requests

connection to remote node

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Register access fail interrupt when the PHY

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Cable power presence monitoring

SCLK is not active

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Separate cable bias (TPBIAS) for each port

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PCI power-management D0, D1, D2, and D3

•

1.8-V core logic with universal PCI interfaces

power states

compatible with 3.3-V and 5-V PCI signaling

•

Initial bandwidth available and initial

environments

channels available registers

•

Physical write posting of up to three

•

PME support per 1394 Open Host Controller

outstanding transactions

Interface Specification

•

PCI burst transfers and deep FIFOs to

NOTE:

Implements technology covered by one or more patents

tolerate large host latency

of Apple Computer, Incorporated and SGS Thompson,

Limited.

•

PCI_CLKRUN protocol

•

External cycle timer control for customized

synchronization

•

Extended resume signaling for compatibility

with legacy DV components

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Copyright © 2006, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.