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TSB12LV32

TSB12LV32I

SLLA215 – JUNE 2006

IEEE 1394-1995 and P1394a Compliant General-Purpose Link-Layer Controller for

Computer Peripherals and Consumer Audio/Video Electronics

•

Programmable Microcontroller Interface With

8-Bit or 16-Bit Data Bus, Multiple Modes of

•

Compliant With IEEE 1394-1995 Standards

Operation Including Burst Mode, and Clock

and 1394a-2000 Supplement for High

Frequency to 60 MHz

•

8-Bit or 16-Bit Data-Mover Port (DM Port)

•

Supports Transfer Rates of 400, 200, or 100

Supports Isochronous, Asynchronous, and

Mbps

Asynchronous Streaming Transmit/Receive

•

Compatible With Texas Instruments Physical

From an Unbuffered Port at a Clock

Layer Controllers (Phys)

Frequency of 25 MHz.

•

Supports the Texas Instruments Bus Holder

•

Backward Compatible With All

Galvanic Isolation Barrier

TSB12LV31(GPLynx) Microcontroller and

•

Glueless Interface to 68000 and ColdFire

Data-Mover Functionality in Hardware

Microcontrollers/Microprocessors

•

Two-Channel Support for Isochronous

•

Supports ColdFire Burst Transfers

Receive to Unbuffered 8/16 Data-Mover Port

•

2-Kbyte General Receive FIFO (GRF)

•

Four-Channel Support for Isochronous

Accessed Through Microcontroller Interface

Transmit From Unbufferred 8/16 Bit

Supports Asynchronous and Isochronous

Data-Mover Port

Receive.

•

Single 3.3-V Supply Operation With 5-V

•

2-Kbyte Asynchronous Transmit FIFO (ATF)

Tolerance Using 5-V Bias Terminals

Accessed Through Microcontroller Interface

•

High Performance 100-Pin PZ Package

Supports Asynchronous Transmissions.

NOTE:

Implements technology covered by one or more patents

of Apple Computer, Incorporated and SGS Thomson,

Limited.

The TSB12LV32 (GP2Lynx) is a high-performance general-purpose IEEE 1394a-2000 link-layer controller (LLC)

with the capability of transferring data between the 1394 Phy-link interface, an external host controller, and an

external device connected to the data-mover port (local bus interface). The 1394 Phy-link interface provides the

connection to a 1394 physical layer device and is supported by the LLC. The LLC provides the control for

transmitting and receiving 1394 packet data between the microcontroller interface and the Phy-link interface via

internal 2-Kbyte FIFOs at rates up to 400 Mbps. The TSB12LV32 transmits and receives correctly formatted

1394 packets, generates and detects the 1394 cycle start packets, communicates transaction layer transmit

requests to the Phy, and generates and inspects the 32-bit cyclic redundancy check (CRC).

The TSB12LV32 is capable of being 1394 cycle master (CM), 1394 bus manager, 1394 isochronous resource

manager (IRM) if additional control status registers (CSRs) are added via the external host controller, and

supports reception of 1394 isochronous data on two channels and transmission of 1394 isochronous data on

four channels.

The

TSB12LV32

supports

a

direct

interface

to

many

microprocessors/microcontrollers

by

including

programmable endian swapping. TSB12LV32 has a generic 16-/8-bit host bus interface which includes support

for a ColdFireE microcontroller mode at rates up to 60 MHz. The microcontroller interface can operate in byte or

word (16 bit) accesses.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Copyright © 2006, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.