MB86836PBT datasheet(11/82 Pages) FUJITSU

Part #	MB86836PBT

Description	32-bit Embedded Controller

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Manufacturer	FUJITSU [Fujitsu Component Limited.]

Direct Link	http://edevice.fujitsu.com/fmd/en/index.html

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MB86830 Series

11

(Continued)

Symbol

Pin name

I/O

Function

D<31:0>

DATA BUS

I/O

Data bus signal.

This pin provides a bidirectional data bus used for instruction fetch,

data load, and data store operations. Instructions and word data must

be aligned at addresses which are multiples of the number 4.

Half words and double words must be aligned at addresses which are

multiples of the numbers 2 and 8, respectively. D<7:0> and D<15:0>

are used in the 8-bit and 16-bit bus modes, respectively. For use in the

16-bit bus mode, a pull-up resistor must be connected to the data bus

which is not used (D<31:8> for the 8-bit bus and D<31:16> for the 16-

bit bus).

AS#

ADDRESS

STROBE

I/O

Address strobe signal.

This pin outputs the “L” level signal for the first bus cycle. Basically, the

bus cycle starts with the AS# signal asserted and ends up with the

READY# or RDYOUT# signal asserted.

In the bus grant state, the pin serves as an input used for the signals to

actuate the CS generator and wait state generator circuits.

RDWR#

READ/WRITE

BUS

TRANSACTION

I/O

Read/write signal.

This pin outputs the “L” level signal when the current bus cycle is the

write cycle or the “H” level signal when it is the read or idle cycle. The

output level remains at “H” or“L” during the entire bus cycle from the be-

ginning to end.

In the bus grant state, the pin serves as an input used for generating

the DWE0#-DWE3# and DOE# signals to enable the DRAM controller.

The signal at this pin is not used when the DRAM controller is disabled.

BE0#

BE1#

BE2#

BE3#

BYTE ENABLE

O

I/O

O

Bye enable signals.

These pins are used to indicate the bytes valid for in write mode when

the 32-bit bus width is used.

In read mode, all of the BE0# to BE3# signals are asserted regardless

of the data type. For the 8-bit or 16-bit bus width, the BE2# and BE3#

pins output ADR<1> and ADR<0>, respectively.

The BE0# to BE3# pins remain enabled during the bus cycle; the out-

put level during the idle cycle is not guaranteed.

In the bus grant state, the pins enter the High-Z state and, only when

the DRAM controller is on with the 16-bit bus width used, the BE2# pin

serves as the ADR<1> input pin.

(Continued)

Width of

bus

Access type

BE0#

BE1#

BE2#

BE3#

Width of

32-bits

bus

Write

Byte-0 (D<31:24>) *

0

1

Byte-1 (D<23:16>)

1

0

1

Byte-2 (D<15:8>)

1

0

1

Byte-3 (D<7:0>)

1

0

Half word-0(D<31:16>)

0

1

Half word-1(D<15:0>)

1

0

Word

0000

Read

All data types

0

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