TSL2572

LIGHT-TO-DIGITAL CONVERTER

TAOS132 − MARCH 2012

10

r

r

Copyright

E 2012, TAOS Inc.

The LUMENOLOGY

r Company

www.taosinc.com

System State Machine Timing

The system state machine shown in Figure 6 provides an overview of the states and state transitions that

provide system control of the device. This section highlights the programmable features, which affect the state

machine cycle time, and provides details to determine system level timing.

When the power management feature is enabled (WEN), the state machine will transition in turn to the Wait

state. The wait time is determined by WLONG, which extends normal operation by 12

WTIME. The formula to determine the wait time is given in the box associated with the Wait state in Figure 9.

When the ALS feature is enabled (AEN), the state machine will transition through the ALS Init and ALS ADC

states. The ALS Init state takes 2.73 ms, while the ALS ADC time is dependent on the integration time (ATIME).

The formula to determine ALS ADC time is given in the associated box in Figure 9. If an interrupt is generated

as a result of the ALS cycle, it will be asserted at the end of the ALS ADC state and transition to the Sleep state

if SAI is enabled.

Wait

Sleep

Idle

WTIME: 1 ~ 256 steps

WLONG = 0

WLONG = 1

Time:

2.73 ms/step

32.8 ms/step

Range:

2.73 ms ~ 699 ms

32.8 ms ~ 8.39s

Time: 2.73 ms

ATIME: 1 ~ 256 steps

Time: 2.73 ms/step

Range: 2.73 ms ~ 699 ms

INT & SAI

!PON

Note: PON, WEN, AEN, and SAI are fields in the Enable register (0x00).

ALS

Init

WEN

& AEN

ALS

ADC

!WEN

& AEN

Figure 9. Detailed State Diagram