Not Recommended for New Designs

PTB48510

PTB48511

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SLTS219F – FEBRUARY 2004 – REVISED MARCH 2007

Table 1. Adjustment Range and Formula Parameters

PARAMETERS

PTB4851xA

PTB4851xB

PTB48510C

5

12

15

3.5

6.5

7.2

5.5

13.4

16.7

2.495

2.495

2.495

7.5

18.2

22.1

9.09

16.9

16.9

NOTES:

1. A 0.05 W rated resistor may be used. The tolerance should be 1%, with a temperature stability of 100

2. Never connect capacitors to the Vo Adj pin. Capacitance added to this pin can affect the stability of the

regulated output.

3. The overvoltage protection (PTB48511x) is nominally set to 25% above the original output voltage set-

point. Increasing the magnitude of the output voltages reduces the margin between the output voltage and

the overvoltage (OV) protection threshold. This could make the module more sensitive to OV faults, as a

result of random noise and load transients.

Note: An OV fault is a latched condition that shuts down the converter's outputs. The fault can be cleared by

cycling the Enable pin, or by momentarily removing input power to the module.

CONFIGURING THE PTB4850x and PTB4851x DC/DC CONVERTERS FOR DSL APPLICATIONS

When operated as a pair, the PTB4850x and PTB4851x converters are specifically designed to provide all the

required supply voltages for powering xDSL chipsets. The PTB4850x produces two logic voltages. They include

a 3.3-V source for logic and I/O, and a low-voltage for powering a digital signal processor core. The PTB4851x

produces a balanced pair of complementary supply voltages that is required for the xDSL transceiver ICs. When

used together in these types of applications, the PTB4850x and PTB4851x may be configured for power-up

sequencing, and also synchronized to a common switch conversion frequency. Figure 19 shows the required

cross-connects between the two converters to enable these two features.

SWITCHING FREQUENCY SYNCHRONIZATION

Unsynchronized, the difference in switch frequency introduces a beat frequency into the input and output AC

ripple components from the converters. The beat frequency can vary considerably with any slight variation in

either converter’s switch frequency. This results in a variable and undefined frequency spectrum for the ripple

waveforms, which would normally require separate filters at the input of each converter. When the switch

frequency of the converters are synchronized, the ripple components are constrained to the fundamental and

higher. This simplifies the design of the output filters, and allows a common filter to be specified for the treatment

of input ripple.

POWER-UP SEQUENCING

The desired power-up sequence for the AC7 supply voltages requires that the two logic-level voltages from the

PTB4850x converter rise to regulation prior to the two complementary voltages that power the transceiver ICs.

This sequence cannot be assured if the PTB4850x and PTB4851x are allowed to power up independently,

especially if the 48-V input voltage rises relatively slowly. To ensure the desired power-up sequence, the EN Out

pin of the PTB4850x is directly connected to the activelow Enable input of the PTB4851x (see Figure 19). This

allows the PTB4850x to momentarily hold off the outputs from the PTB4851x until the logic-level voltages have

risen first. Figure 19 shows the power-up waveforms of all four supply voltages from the schematic of Figure 19.

Copyright © 2004–2007, Texas Instruments Incorporated

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