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MSP430TCH5E Datasheet(PDF) 9 Page - Texas Instruments |
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MSP430TCH5E Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 68 page  Program Counter PC/R0 Stack Pointer SP/R1 Status Register SR/CG1/R2 Constant Generator CG2/R3 General-Purpose Register R4 General-Purpose Register R5 General-Purpose Register R6 General-Purpose Register R7 General-Purpose Register R8 General-Purpose Register R9 General-Purpose Register R10 General-Purpose Register R11 General-Purpose Register R12 General-Purpose Register R13 General-Purpose Register R15 General-Purpose Register R14 MSP430TCH5E www.ti.com SLAS895 – DECEMBER 2013 Short-Form Description CPU The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand. The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to- register operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator, respectively. The remaining registers are general-purpose registers. Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions. The instruction set consists of the original 51 instructions with three formats and seven address modes and additional instructions for the expanded address range. Each instruction can operate on word and byte data. Instruction Set The instruction set consists of 51 instructions with three formats and seven address modes. Each instruction can operate on word and byte data. Table 3 shows examples of the three types of instruction formats; Table 4 shows the address modes. Table 3. Instruction Word Formats INSTRUCTION FORMAT EXAMPLE OPERATION Dual operands, source-destination ADD R4,R5 R4 + R5 ---> R5 Single operands, destination only CALL R8 PC -->(TOS), R8--> PC Relative jump, un/conditional JNE Jump-on-equal bit = 0 Table 4. Address Mode Descriptions(1) ADDRESS MODE S D SYNTAX EXAMPLE OPERATION Register ✓ ✓ MOV Rs,Rd MOV R10,R11 R10 -- --> R11 Indexed ✓ ✓ MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5) -- --> M(6+R6) Symbolic (PC relative) ✓ ✓ MOV EDE,TONI M(EDE) -- --> M(TONI) Absolute ✓ ✓ MOV &MEM,&TCDAT M(MEM) -- --> M(TCDAT) Indirect ✓ MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) -- --> M(Tab+R6) M(R10) -- --> R11 Indirect autoincrement ✓ MOV @Rn+,Rm MOV @R10+,R11 R10 + 2-- --> R10 Immediate ✓ MOV #X,TONI MOV #45,TONI #45 -- --> M(TONI) (1) S = source, D = destination Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: MSP430TCH5E |
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