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MB91108PFV Datasheet(PDF) 6 Page - Fujitsu Component Limited. |
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MB91108PFV Datasheet(HTML) 6 Page - Fujitsu Component Limited. |
6 / 96 page MB91107/108 6 (Continued) Pin no. Pin name Circuit type Function 80 BGRNT/P81 F External bus release acknowledge output. Outputs “L” level when external bus is released. Can be configured as a port when this pin is not used. 81 BRQ/P82 P External bus release request input. Inputs “1” when release of external bus is required. Can be configured as a port when this pin is not used. 82 RD M Read strobe output pin for external bus. 83 WR0 M Write strobe output pin for external bus. Relation between control signals and effective byte locations is as follows: Note: WR1 is Hi-Z during resetting. Attach an external pull-up resister when using at 16-bit bus width. 84 WR1/P85 F 65 CS0 M Chip select 0 output (“L” active). 66 67 68 69 70 CS1/PA1 CS2/PA2 CS3/PA3 CS4/PA4 CS5/PA5 F Chip select 1 output (“L” active). Chip select 2 output (“L” active). Chip select 3 output (“L” active). Chip select 4 output (“L” active). Chip select 5 output (“L” active). Can be configured as ports when PA1 to PA5 are not used. 71 CLK/PA6 F System clock output. Outputs clock signal of external bus operating frequency. Can be configured as a port when PA6 is not used. 56 57 58 59 60 61 62 63 RAS0/PB0 CS0L/PB1 CS0H/PB2 DW0/PB3 RAS1/PB4 CS1L/PB5 CS1H/PB6 DW1/PB7 F RAS output for DRAM bank 0. CASL output for DRAM bank 0. CASH output for DRAM bank 0. WE output for DRAM bank 0 (“L” active). RAS output for DRAM bank 1. CASL output for DRAM bank 1. CASH output for DRAM bank 1. WE output for DRAM bank 1 (“L” active) Can be configured as a port when PB0 to PB7 are not used. 76 77 78 MD0 MD1 MD2 G Mode pins 0 to 2. MCU basic operation mode is set by these pins. Directly connect these pins with VCC or VSS for use. 53 54 X1 X0 A Clock (oscillator) output. Clock (oscillator) input. 74 RST B External reset input. 73 HST H Hardware standby input (“L” active). 16-bit bus width 8-bit bus width D31 to D24 WR0 WR0 D23 to D16 WR1 (I/O port enabled) Refer to the DRAM interface for details. |
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