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MBM29DL800TA-70 Datasheet(PDF) 1 Page - Fujitsu Component Limited. |
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MBM29DL800TA-70 Datasheet(HTML) 1 Page - Fujitsu Component Limited. |
1 / 59 page DS05-20860-3E FUJITSU SEMICONDUCTOR DATA SHEET FLASH MEMORY CMOS 8M (1M × 8/512K × 16) BIT MBM29DL800TA-70/-90/-12/MBM29DL800BA-70/-90/-12 s FEATURES • Single 3.0 V read, program, and erase Minimizes system level power requirements • Simultaneous operations Read-while-Erase or Read-while-Program • Compatible with JEDEC-standard commands Uses same software commands as E2PROMs • Compatible with JEDEC-standard world-wide pinouts (Pin compatible with MBM29LV800TA/BA) 48-pin TSOP(I) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type) 48-ball FBGA (Package suffix: PBT) • Minimum 100,000 program/erase cycles • High performance 70 ns maximum access time • Sector erase architecture Two 16K byte, four 8K bytes, two 32K byte, and fourteen 64K bytes. Any combination of sectors can be concurrently erased. Also supports full chip erase. • Boot Code Sector Architecture T = Top sector B = Bottom sector • Embedded EraseTM Algorithms Automatically pre-programs and erases the chip or any sector • Embedded ProgramTM Algorithms Automatically writes and verifies data at specified address •Data Polling and Toggle Bit feature for detection of program or erase cycle completion • Ready/Busy output (RY/BY) Hardware method for detection of program or erase cycle completion • Automatic sleep mode When addresses remain stable, automatically switch themselves to low power mode. •Low VCC write inhibit ≤ 2.5 V • Erase Suspend/Resume Suspends the erase operation to allow a read in another sector within the same device (Continued) Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc. |
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