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MSP430F2011TN Datasheet(PDF) 9 Page - Texas Instruments |
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MSP430F2011TN Datasheet(HTML) 9 Page - Texas Instruments |
9 / 94 page MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 Table 3. Terminal Functions, MSP430F20x2 TERMINAL NO. DESCRIPTION NAME I/O PW, N RSA General-purpose digital I/O pin Timer_A, clock signal TACLK input P1.0/TACLK/ACLK/A0 2 1 I/O ACLK signal output ADC10 analog input A0 General-purpose digital I/O pin P1.1/TA0/A1 3 2 I/O Timer_A, capture: CCI0A input, compare: Out0 output ADC10 analog input A1 General-purpose digital I/O pin P1.2/TA1/A2 4 3 I/O Timer_A, capture: CCI1A input, compare: Out1 output ADC10 analog input A2 General-purpose digital I/O pin ADC10 conversion clock output P1.3/ADC10CLK/A3/ 5 4 I/O ADC10 analog input A3 VREF-/VeREF- Input for negative external reference voltage/negative internal reference voltage output General-purpose digital I/O pin SMCLK signal output P1.4/SMCLK/A4/VREF+/ ADC10 analog input A4 6 5 I/O VeREF+/TCK Input for positive external reference voltage/positive internal reference voltage output JTAG test clock, input terminal for device programming and test General-purpose digital I/O pin Timer_A, compare: Out0 output P1.5/TA0/A5/SCLK/TMS 7 6 I/O ADC10 analog input A5 USI: external clock input in SPI or I2C mode; clock output in SPI mode JTAG test mode select, input terminal for device programming and test General-purpose digital I/O pin Timer_A, capture: CCI1B input, compare: Out1 output P1.6/TA1/A6/SDO/SCL/ 8 7 I/O ADC10 analog input A6 TDI/TCLK USI: Data output in SPI mode; I2C clock in I2C mode JTAG test data input or test clock input during programming and test General-purpose digital I/O pin P1.7/A7/SDI/SDA/ ADC10 analog input A7 9 8 I/O TDO/TDI(1) USI: Data input in SPI mode; I2C data in I2C mode JTAG test data output terminal or test data input during programming and test Input terminal of crystal oscillator XIN/P2.6/TA1 13 12 I/O General-purpose digital I/O pin Timer_A, compare: Out1 output Output terminal of crystal oscillator XOUT/P2.7 12 11 I/O General-purpose digital I/O pin(2) Reset or nonmaskable interrupt input RST/NMI/SBWTDIO 10 9 I Spy-Bi-Wire test data input/output during programming and test Selects test mode for JTAG pins on Port 1. The device protection fuse is TEST/SBWTCK 11 10 I connected to TEST. Spy-Bi-Wire test clock input during programming and test VCC 1 NA Supply voltage VSS 14 NA Ground reference DVCC NA 16 Digital supply voltage AVCC NA 15 Analog supply voltage DVSS NA 14 Digital ground reference AVSS NA 13 Analog ground reference QFN Pad NA Pad NA QFN package pad. Connection to VSS is recommended. (1) TDO or TDI is selected via JTAG instruction. (2) If XOUT/P2.7 is used as an input, excess current flows until P2SEL.7 is cleared. This is due to the oscillator output driver connection to this pad after reset. Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback 9 |
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