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MSP430F2121IDW Datasheet(PDF) 5 Page - Texas Instruments |
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MSP430F2121IDW Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 62 page  MSP430F21x1 www.ti.com SLAS439F – SEPTEMBER 2004 – REVISED AUGUST 2011 Table 2. Terminal Functions TERMINAL NO. DW, I/O DESCRIPTION NAME PW, RGE or DGV General-purpose digital I/O pin P1.0/TACLK 13 13 I/O Timer_A, clock signal TACLK input General-purpose digital I/O pin P1.1/TA 14 14 I/O Timer_A, capture: CCI0A input, compare: Out0 output/BSL transmit General-purpose digital I/O pin P1.2/TA1 15 15 I/O Timer_A, capture: CCI1A input, compare: Out1 output General-purpose digital I/O pin P1.3/TA2 16 16 I/O Timer_A, capture: CCI2A input, compare: Out2 output General-purpose digital I/O pin / SMCLK signal output P1.4/SMCLK/TCK 17 17 I/O Test Clock input for device programming and test General-purpose digital I/O pin / Timer_A, compare: Out0 output P1.5/TA/TMS 18 18 I/O Test Mode Select input for device programming and test General-purpose digital I/O pin / Timer_A, compare: Out1 output P1.6/TA1/TDI/TCLK 19 20 I/O Test Data Input or Test Clock Input for programming and test General-purpose digital I/O pin / Timer_A, compare: Out2 output P1.7/TA2/TDO/TDI(1) 20 21 I/O Test Data Output or Test Data Input for programming and test General-purpose digital I/O pin / ACLK output P2.0/ACLK/CA2 8 6 I/O Comparator_A+, CA2 input General-purpose digital I/O pin / Timer_A, clock signal at INCLK P2.1/INCLK/CA3 9 7 I/O Comparator_A+, CA3 input General-purpose digital I/O pin P2.2/CAOUT/TA/CA4 10 8 I/O Timer_A, capture: CCI0B input/BSL receive Comparator_A+, output / CA4 input General-purpose digital I/O pin / Timer_A, compare: Out1 output P2.3/CA0/TA1 11 10 I/O Comparator_A+, CA0 input General-purpose digital I/O pin / Timer_A, compare: Out2 output P2.4/CA1/TA2 12 11 I/O Comparator_A+, CA1 input General-purpose digital I/O pin P2.5/CA5 3 24 I/O Comparator_A+, CA5 input Input terminal of crystal oscillator XIN/P2.6/CA6 6 4 I/O General-purpose digital I/O pin Comparator_A+, CA6 input Output terminal of crystal oscillator XOUT/P2.7/CA7(2) 5 3 I/O General-purpose digital I/O pin Comparator_A+, CA7 input RST/NMI 7 5 I Reset or nonmaskable interrupt input Selects test mode for JTAG pins on Port1. The device protection fuse is connected to TEST 1 22 I TEST. VCC 2 23 Supply voltage VSS 4 2 Ground reference QFN Pad NA Pad NA QFN package thermal pad. Connect to VSS. (1) TDO or TDI is selected via JTAG instruction. (2) If XOUT/P2.7/CA7 is used as an input, excess current will flow until P2SEL.7 is cleared. This is due to the oscillator output driver connection to this pad after reset. Copyright © 2004–2011, Texas Instruments Incorporated 5 |
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