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MF10-N Datasheet(PDF) 4 Page - Texas Instruments

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Part # MF10-N
Description  MF10-N Universal Monolithic Dual Switched Capacitor Filter
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

MF10-N Datasheet(HTML) 4 Page - Texas Instruments

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MF10-N
SNOS547C – JUNE 1999 – REVISED APRIL 2013
www.ti.com
Electrical Characteristics (continued)
V
+ = +5.00V and V= −5.00V unless otherwise specified. Boldface limits apply for T
MIN to TMAX; all other limits TA = TJ =
25°C.
MF10ACN, MF10CCN,
MF10CCWM
Symbol
Parameter
Conditions
Units
Tested
Design
Typical(1)
Limit(2)
Limit (3)
Vpin12 = +5V, (fCLK/fO = 50)
83
dB
Dynamic Range(6)
Vpin12 = 0V, (fCLK/fO = 100)
80
dB
ISC
Source
20
mA
Maximum Output Short Circuit
Current(7)
Sink
3.0
mA
(6)
For ±5V supplies the dynamic range is referenced to 2.82V rms (4V peak) where the wideband noise over a 20 kHz bandwidth is
typically 200
μV rms for the MF10-N with a 50:1 CLK ratio and 280 μV rms for the MF10-N with a 100:1 CLK ratio.
(7)
The short circuit source current is measured by forcing the output that is being tested to its maximum positive voltage swing and then
shorting that output to the negative supply. The short circuit sink current is measured by forcing the output that is being tested to its
maximum negative voltage swing and then shorting that output to the positive supply. These are the worst case conditions.
Logic Input Characteristics
Boldface limits apply for TMIN to TMAX; all other limits TA = TJ = 25°C
MF10ACN, MF10CCN, MF10CCWM
Parameter
Conditions
Units
Tested
Design
Typical(1)
Limit(2)
Limit(3)
Min Logical “1”
+3.0
+3.0
V
V+ = +5V, V=
−5V, VLSh = 0V
Max Logical “0”
−3.0
−3.0
V
CMOS Clock Input
Voltage
Min Logical “1”
+8.0
+8.0
V
V+ = +10V, V= 0V, VLSh = +5V
Max Logical “0”
+2.0
+2.0
V
Min Logical “1”
+2.0
+2.0
V
V+ = +5V, V=
−5V, VLSh = 0V
Max Logical “0”
+0.8
+0.8
V
TTL Clock Input
Voltage
Min Logical “1”
+2.0
+2.0
V
V+ = +10V, V= 0V, VLSh = 0V
Max Logical “0”
+0.8
+0.8
V
(1)
Typicals are at 25°C and represent most likely parametric norm.
(2)
Tested limits are ensured to AOQL (Average Outgoing Quality Level).
(3)
Design limits are specified but not 100% tested. These limits are not used to calculate outgoing quality levels.
4
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Copyright © 1999–2013, Texas Instruments Incorporated
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