LMH0056

SNLS236C – AUGUST 2006 – REVISED APRIL 2013

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DEVICE DESCRIPTION

The LMH0056 HD/SD SDI Reclocker with 4:1 Input Multiplexer is used in many types of digital video signal

processing equipment. Supported serial digital video standards are SMPTE 259M (A & C) and SMPTE 292M.

Corresponding serial data rates are 143 Mbps, 270 Mbps, 1.483 Gbps and 1.485 Gbps. DVB-ASI data at 270

Mbps may also be retimed. The LMH0056 retimes the serial data stream to suppress accumulated jitter. It

provides two low-jitter, differential, serial data outputs. The second output may be selected to output either serial

data or a low-jitter serial data-rate clock. Controls and indicators are: serial data-rate clock or second serial data

output select, manual rate select input, SD/HD rate output, lock detect output, auto/manual data bypass and

output mute.

Serial data inputs are CML and LVPECL compatible. Serial data and data-rate clock outputs are differential CML

and produce LVPECL compatible levels. The output buffer design can drive AC or DC-coupled, terminated 100

Ω

Logic inputs and outputs are LVCMOS compatible.

The device package is a 48–pin WQFN with an exposed die attach pad. The exposed die attach pad is

terminal must be connected to the negative power supply or circuit ground.

Serial Data Inputs, Serial Data and Clock Outputs

SERIAL DATA INPUT AND OUTPUTS

The differential serial data inputs, SDI0-SDI3, accept serial digital video data at the rates specified in Table 1.

The serial data inputs are differential LVPECL compatible. These inputs are intended to be DC interfaced to

devices such as the LMH0034 adaptive cable equalizer. These inputs are not internally terminated or biased.

The inputs may be AC-coupled if a suitable input bias voltage is provided.

The LMH0056 provides four independent, multiplexed data inputs. The active input channel is selected via the

SEL0 and SEL1 pins, as shown in Table 2. Figure 2 shows the equivalent input circuit for SDI[3:0] and SDI[3:0].

The LMH0056 has two, retimed, differential, serial data outputs, SDO and SCO/SDO2. These outputs provide

low jitter, differential, retimed data to devices such as the LMH0002 cable driver or the LMH0031 deserializer.

Output SCO/SDO2 is multiplexed and can provide either a second serial data output or a serial data-rate clock

output. Figure 3 shows the equivalent output circuit for SDO, SDO, SCO/SDO2, and SCO/SDO2.

The SCO_EN input controls the operating mode for the SCO/SDO2 output. When the SCO_EN input is high the

SCO/SDO2 output provides a serial data-rate clock. When SCO_EN is low, the SCO/SDO2 output provides

retimed serial data.

Both differential serial data outputs, SDO and SCO/SDO2, are muted when the MUTE input is a logic low level.

SCO/SDO2 also mutes when the Bypass mode is activated when this output is operating as the serial clock

output. When muted, SDO and SDO (or SDO2 and SDO2) will assume opposite differential output levels. The

CML serial data outputs are differential LVPECL compatible. These outputs have internal 50

Ω pull-ups and are

suitable for driving AC or DC-coupled, 100

Ω center-tapped, AC grounded or 100Ω un-center-tapped, differentially

terminated networks.

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